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Strain-Engineered MOSFETs
architecture in combination with the small dimensions of the devices helps
to improve the on-state drive current and reduce the off-state leakage current. These advantages translate to lower power consumption and enhanced
device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density, which translates
to smaller overall microelectronics.
The limitation of the downscaling of single-gate, planar bulk MOSFETs
is the inherent poor electrostatic control of the gate over the channel and
poor transport properties of the carrier. Therefore, it is imperative to find a
solution that encompasses materials to a new architecture for future technology nodes. Device structures are being scaled from 3D (bulk CMOS),
quasi 2D (partially depleted SOI), 2D (fully depleted SOI), and quasi 1D
(nanowire FET and tri-gate FinFET) for better channel electrostatics. To
reduce the short-channel effects, researchers have proposed double-gate
MOSFETs and FinFET devices. In tri-gate devices the gate is placed on the
three sides of the channel. This results in a better control on the channel
and significant reduction in the drain-to-source subthreshold leakage current. Many novel device structures and materials such as silicon nanowire
transistors, carbon nanotube FETs, and molecular transistors have been
proposed.
There are several ways by which the device engineer can handle the SCE,
including reduction of S/D junction depth, increasing dopant concentration in the channel, and decreasing the effective oxide thickness (EOT) of
the gate dielectric. Reducing EOT results in increased capacitive coupling
between the gate electrode and channel region. This implies a greater ease
in altering the surface potential at the dielectric/channel interface that
leads to inversion. EOT scaling progressed for many years simply by reducing the thickness of the gate dielectric, thereby increasing its capacitance.
In order to control short-channel effects in aggressively scaled MOSFETs,
one must ensure also that the ratio of body thickness to gate length is sufficient to ensure both low off-state leakage and full gate control over the
channel. Decreasing the S/D junction depth and increasing dopant concentration in the channel are the techniques that are almost exclusively
applied in planar MOSFET fabrication. In order to suppress the SCE in
bulk MOSFETs, other parameters need to be scaled down together with L g ,
such as the gate oxide thickness (T ox ), the channel depletion width (X d ), and
the source/drain junction depth (X j ). However, the thickness of SiO 2 -based
gate dielectrics is approaching physical limits (<2 nm), for which quantum
mechanical tunneling induces severe gate leakage current through the gate
dielectric. The off-state leakage current (I off ) increases as gate length (L g )
decreases because capacitive control of the channel potential by the gate
becomes more difficult. Metal gate technology offers tunable work function
for V th adjustment and allows further MOSFET scaling because it eliminates the issues of poly-Si gate technology, namely, the gate depletion effect
and boron penetration.
Strain-Engineered MOSFETs
architecture in combination with the small dimensions of the devices helps
to improve the on-state drive current and reduce the off-state leakage current. These advantages translate to lower power consumption and enhanced
device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density, which translates
to smaller overall microelectronics.
The limitation of the downscaling of single-gate, planar bulk MOSFETs
is the inherent poor electrostatic control of the gate over the channel and
poor transport properties of the carrier. Therefore, it is imperative to find a
solution that encompasses materials to a new architecture for future technology nodes. Device structures are being scaled from 3D (bulk CMOS),
quasi 2D (partially depleted SOI), 2D (fully depleted SOI), and quasi 1D
(nanowire FET and tri-gate FinFET) for better channel electrostatics. To
reduce the short-channel effects, researchers have proposed double-gate
MOSFETs and FinFET devices. In tri-gate devices the gate is placed on the
three sides of the channel. This results in a better control on the channel
and significant reduction in the drain-to-source subthreshold leakage current. Many novel device structures and materials such as silicon nanowire
transistors, carbon nanotube FETs, and molecular transistors have been
proposed.
There are several ways by which the device engineer can handle the SCE,
including reduction of S/D junction depth, increasing dopant concentration in the channel, and decreasing the effective oxide thickness (EOT) of
the gate dielectric. Reducing EOT results in increased capacitive coupling
between the gate electrode and channel region. This implies a greater ease
in altering the surface potential at the dielectric/channel interface that
leads to inversion. EOT scaling progressed for many years simply by reducing the thickness of the gate dielectric, thereby increasing its capacitance.
In order to control short-channel effects in aggressively scaled MOSFETs,
one must ensure also that the ratio of body thickness to gate length is sufficient to ensure both low off-state leakage and full gate control over the
channel. Decreasing the S/D junction depth and increasing dopant concentration in the channel are the techniques that are almost exclusively
applied in planar MOSFET fabrication. In order to suppress the SCE in
bulk MOSFETs, other parameters need to be scaled down together with L g ,
such as the gate oxide thickness (T ox ), the channel depletion width (X d ), and
the source/drain junction depth (X j ). However, the thickness of SiO 2 -based
gate dielectrics is approaching physical limits (<2 nm), for which quantum
mechanical tunneling induces severe gate leakage current through the gate
dielectric. The off-state leakage current (I off ) increases as gate length (L g )
decreases because capacitive control of the channel potential by the gate
becomes more difficult. Metal gate technology offers tunable work function
for V th adjustment and allows further MOSFET scaling because it eliminates the issues of poly-Si gate technology, namely, the gate depletion effect
and boron penetration.