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Preface
strain-engineered devices, technology CAD and reliability of strain-engineered MOSFETs, process compact modelling, and process-aware design of
strain-engineered MOSFETs, and looks beyond the 22 nm node.
Several excellent books and monographs have appeared on multigate
MOSFETs, high-mobility substrates, and Ge microelectronics and strained
semiconductor physics. Numerous papers have appeared on strained Si
and process-induced strain, but there is a lack of a single text that combines both the strain-engineered MOSFETs and their modelling using
technology computer-aided design. We attempt to summarise some of
the latest efforts to reveal the advantages that strain has brought in the
development of strain-engineered MOSFETs. We have included important works as well as our own research and ideas by the research community, and due to space limitations, we have referred to only representative
papers and listed books recently published in related areas for additional
reading.
The book is mainly meant for final-year undergraduate and postgraduate students, scientists, and engineers involved in research and development
of high-performance MOSFET devices and circuits. We hope this book will
help in process technology development and design of strain-engineered
MOSFETs. It may also serve as a reference book on strain-engineered heterostructure MOSFETs for active researchers in this field.
We thank Chhandak Mukherjee for contributing to Chapter 6.
C. K. Maiti and T. K. Maiti
Kharagpur, India