85
Process-Induced Stress Engineering in CMOS Technology
References
1. C. K. Maiti, S. Chattopadhyay, and L. K. Bera, Strained-Si Heterostructure FieldEffect Devices, CRC Press (Taylor & Francis), Boca Raton, FL, 2007.
2. S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman,
J. Klaus, Z. Ma, M. Bohr, and Y. El-Mansy. A 90nm Logic Technology Featuring
Strained-Silicon, IEEE Trans. Electron Dev., 51, 1790–1797, 2004.
3. S. E. Thompson, G. Sun, Y. Choi, and T. Nishida, Uniaxial-Process-Induced
Strained-Si: Extending the CMOS Roadmap, IEEE Trans. Electron. Dev., 53, 1010–
1020, 2006.
4. H. H. Hall, J. Bardeen, and G. L. Pearson, The Effects of Pressure and Temperature
on the Resistance of Junctions in Germanium, Phys. Rev., 84, 129–132, 1951.
5. C. S. Smith, Piezoresistance Effect in Germanium and Silicon, Phys. Rev., 94,
42–49, 1954.
6. J. Welser, J. L. Hoyt, and J. F. Gibbons, NMOS and PMOS Transistors Fabricated
in Strained Silicon/Relaxed Silicon-Germanium Structures, IEEE IEDM Tech.
Dig., 1000–1002, 1992.
7. J. Welser, J. L. Hoyt, and J. F. Gibbons, Electron Mobility Enhancement in
Strained-Si N-Type Metal-Oxide-Semiconductor Field-Effect Transistors, IEEE
Electron Device Lett., 15, 100–102, 1994.
8. P. Verheyen, N. Collaert, R. Rooyackers, R. Loo, D. Shamiryan, A. De
Keersgieter, G. Eneman, F. Leys, A. Dixit, M. Goodwin, Y. S. Yim, M. Caymax,
K. De Meyer, P. Absil, M. Jurczak, and S. Biesemans, 25% Drive Current
Improvement for p-Type Multiple Gate FET (MuGFET) Devices by the
Introduction of Recessed Si 0.8 Ge 0.2 in the Source and Drain Regions, Proc.
Symp. VLSI Technol., 194–195, 2005.
9. P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise,
Fundamentals of Silicon Material Properties for Successful Exploitation of
Strain Engineering in Modern CMOS Manufacturing, IEEE Trans. Electron Dev.,
53, 944–964, 2006.
10. H. Tsuno, K. Anzai, M. Matsumura, S. Minami, A. Honjo, H. Koike, Y. Hiura, A.
Takeo, W. Fu,Y. Fukuzaki, M. Kanno, H. Ansai, and N. Nagashima, Advanced
Analysis and Modelling of MOSFET Characteristic Fluctuation Caused by
Layout Variation, Proc. Symp. VLSI Technol., 204–205, 2007.
11. K. Takahashi and M. Sekiguchi, Through Silicon Via and 3-D Wafer/Chip
Stacking Technology, Proc. Symp. VLSI Circuits, 89–92, 2006.
12. K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, Thermo-Mechanical
Reliability of 3-D ICs Containing Through Silicon Vias, Proc. IEEE Electronic
Components Technol. Conf., 630–634, 2009.
13. C. S. Selvanayagam, X. Zhang, R. Rajoo, and D. Pinjala, Modelling Stress in
Silicon with TSVs and Its Effect on Mobility, Proc. IEEE Electronics Packaging
Technol. Conf., 612–618, 2009.
14. N. H. Khan, Through-Silicon Via Analysis for the Design of 3-D Integrated
Circuits, PhD thesis, Tufts University, 2011.
15. L. Yu, A Study of Through-Silicon-Via (TSV) Induced Transistor Variation,
Master of Science thesis, Massachusetts Institute of Technology, 2011.
Process-Induced Stress Engineering in CMOS Technology
References
1. C. K. Maiti, S. Chattopadhyay, and L. K. Bera, Strained-Si Heterostructure FieldEffect Devices, CRC Press (Taylor & Francis), Boca Raton, FL, 2007.
2. S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman,
J. Klaus, Z. Ma, M. Bohr, and Y. El-Mansy. A 90nm Logic Technology Featuring
Strained-Silicon, IEEE Trans. Electron Dev., 51, 1790–1797, 2004.
3. S. E. Thompson, G. Sun, Y. Choi, and T. Nishida, Uniaxial-Process-Induced
Strained-Si: Extending the CMOS Roadmap, IEEE Trans. Electron. Dev., 53, 1010–
1020, 2006.
4. H. H. Hall, J. Bardeen, and G. L. Pearson, The Effects of Pressure and Temperature
on the Resistance of Junctions in Germanium, Phys. Rev., 84, 129–132, 1951.
5. C. S. Smith, Piezoresistance Effect in Germanium and Silicon, Phys. Rev., 94,
42–49, 1954.
6. J. Welser, J. L. Hoyt, and J. F. Gibbons, NMOS and PMOS Transistors Fabricated
in Strained Silicon/Relaxed Silicon-Germanium Structures, IEEE IEDM Tech.
Dig., 1000–1002, 1992.
7. J. Welser, J. L. Hoyt, and J. F. Gibbons, Electron Mobility Enhancement in
Strained-Si N-Type Metal-Oxide-Semiconductor Field-Effect Transistors, IEEE
Electron Device Lett., 15, 100–102, 1994.
8. P. Verheyen, N. Collaert, R. Rooyackers, R. Loo, D. Shamiryan, A. De
Keersgieter, G. Eneman, F. Leys, A. Dixit, M. Goodwin, Y. S. Yim, M. Caymax,
K. De Meyer, P. Absil, M. Jurczak, and S. Biesemans, 25% Drive Current
Improvement for p-Type Multiple Gate FET (MuGFET) Devices by the
Introduction of Recessed Si 0.8 Ge 0.2 in the Source and Drain Regions, Proc.
Symp. VLSI Technol., 194–195, 2005.
9. P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise,
Fundamentals of Silicon Material Properties for Successful Exploitation of
Strain Engineering in Modern CMOS Manufacturing, IEEE Trans. Electron Dev.,
53, 944–964, 2006.
10. H. Tsuno, K. Anzai, M. Matsumura, S. Minami, A. Honjo, H. Koike, Y. Hiura, A.
Takeo, W. Fu,Y. Fukuzaki, M. Kanno, H. Ansai, and N. Nagashima, Advanced
Analysis and Modelling of MOSFET Characteristic Fluctuation Caused by
Layout Variation, Proc. Symp. VLSI Technol., 204–205, 2007.
11. K. Takahashi and M. Sekiguchi, Through Silicon Via and 3-D Wafer/Chip
Stacking Technology, Proc. Symp. VLSI Circuits, 89–92, 2006.
12. K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, Thermo-Mechanical
Reliability of 3-D ICs Containing Through Silicon Vias, Proc. IEEE Electronic
Components Technol. Conf., 630–634, 2009.
13. C. S. Selvanayagam, X. Zhang, R. Rajoo, and D. Pinjala, Modelling Stress in
Silicon with TSVs and Its Effect on Mobility, Proc. IEEE Electronics Packaging
Technol. Conf., 612–618, 2009.
14. N. H. Khan, Through-Silicon Via Analysis for the Design of 3-D Integrated
Circuits, PhD thesis, Tufts University, 2011.
15. L. Yu, A Study of Through-Silicon-Via (TSV) Induced Transistor Variation,
Master of Science thesis, Massachusetts Institute of Technology, 2011.