86
Strain-Engineered MOSFETs
16. C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. C.
Chai, Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through
Silicon Via) and Their Flip-Chip Microbumps, IEEE Trans. Adv. Packaging, 32,
720–728, 2009.
17. B. Wunderle, R. Mrossko, O.Wittler, E. Kaulfersch, P. Ramm, B. Michel, and
H. Reichl, Thermo-Mechanical Reliability of 3-D-Integrated Microstructures in
Stacked Silicon, Proc. Mater. Res. Soc. Symp., 67, 970–974, 2007.
18. T. Chidambaram, C. McDonough, R. Geer, and W. Wang, TSV Stress Testing and
Modelling for 3D IC Applications, Proc. Physical Failure Anal. Integrated Circuits,
727–730, 2009.
19. K. H. Lu, Thermo-Mechanical Reliability of 3-D Interconnects Containing
Through-Silicon-Vias (TSVs), PhD thesis, University of Texas at Austin, 2010.
20. C. J. McDonough, Applications of Raman Spectroscopy for Silicon Stress
Characterization in Integrated Circuits, PhD thesis, University at Albany, State
University of New York, 2011.
21. Y. Yang, G. Katti, R. Labie, Y. Travaly, B. Verlinden, and I. De Wolf, Electrical
Evaluation of 130-nm MOSFETs with TSV Proximity in 3D-SIC Structure, Proc.
Interconnect Technology Conf. (IITC), 1–3, 2010.
22. S. Ryu, K. Lu, X. Zhang, J. Im, P. Ho, and R. Huang, Impact of Near-Surface
Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D
Interconnects, IEEE Trans. Dev. Mater. Reliab., 11, 35–43, 2011.
23. J. H. Lau, Evolution and Outlook of TSV and 3D IC/Si Integration, Proc. 12th
Electronics Packaging Technology Conf., 560–570, 2010.
24. N. Tanaka, M. Kawashita, Y. Yoshimura, T. Uematsu, M. Fujisawa, H. Shimokawa,
N. Kinoshita, T. Naito, T. Kikuchi, and T. Akazawa, Characterization of MOS
Transistors after TSV Fabrication and 3D-Assembly, Proc. 2nd Electronics Syst.
Integration, 131–134, 2008.
25. A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas,
S. Domae, D. Perry, M. Choi, A. Redolfi, C. Okoro, Y. Yang, J. Van Olmen, S.
Thangaraju, D. Tezcan, P. Soussan, J. Cho, A. Yakovlev, P. Marchal, Y. Travaly,
E. Beyne, S. Biesemans, and B. Swinnen, Comprehensive Analysis of the Impact
of Single and Arrays of Through Silicon Vias Induced Stress on High-k/Metal
Gate CMOS Performance, IEEE IEDM Tech. Dig., 2.2.1–2.2.4, 2010.
Strain-Engineered MOSFETs
16. C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. C.
Chai, Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through
Silicon Via) and Their Flip-Chip Microbumps, IEEE Trans. Adv. Packaging, 32,
720–728, 2009.
17. B. Wunderle, R. Mrossko, O.Wittler, E. Kaulfersch, P. Ramm, B. Michel, and
H. Reichl, Thermo-Mechanical Reliability of 3-D-Integrated Microstructures in
Stacked Silicon, Proc. Mater. Res. Soc. Symp., 67, 970–974, 2007.
18. T. Chidambaram, C. McDonough, R. Geer, and W. Wang, TSV Stress Testing and
Modelling for 3D IC Applications, Proc. Physical Failure Anal. Integrated Circuits,
727–730, 2009.
19. K. H. Lu, Thermo-Mechanical Reliability of 3-D Interconnects Containing
Through-Silicon-Vias (TSVs), PhD thesis, University of Texas at Austin, 2010.
20. C. J. McDonough, Applications of Raman Spectroscopy for Silicon Stress
Characterization in Integrated Circuits, PhD thesis, University at Albany, State
University of New York, 2011.
21. Y. Yang, G. Katti, R. Labie, Y. Travaly, B. Verlinden, and I. De Wolf, Electrical
Evaluation of 130-nm MOSFETs with TSV Proximity in 3D-SIC Structure, Proc.
Interconnect Technology Conf. (IITC), 1–3, 2010.
22. S. Ryu, K. Lu, X. Zhang, J. Im, P. Ho, and R. Huang, Impact of Near-Surface
Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D
Interconnects, IEEE Trans. Dev. Mater. Reliab., 11, 35–43, 2011.
23. J. H. Lau, Evolution and Outlook of TSV and 3D IC/Si Integration, Proc. 12th
Electronics Packaging Technology Conf., 560–570, 2010.
24. N. Tanaka, M. Kawashita, Y. Yoshimura, T. Uematsu, M. Fujisawa, H. Shimokawa,
N. Kinoshita, T. Naito, T. Kikuchi, and T. Akazawa, Characterization of MOS
Transistors after TSV Fabrication and 3D-Assembly, Proc. 2nd Electronics Syst.
Integration, 131–134, 2008.
25. A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas,
S. Domae, D. Perry, M. Choi, A. Redolfi, C. Okoro, Y. Yang, J. Van Olmen, S.
Thangaraju, D. Tezcan, P. Soussan, J. Cho, A. Yakovlev, P. Marchal, Y. Travaly,
E. Beyne, S. Biesemans, and B. Swinnen, Comprehensive Analysis of the Impact
of Single and Arrays of Through Silicon Vias Induced Stress on High-k/Metal
Gate CMOS Performance, IEEE IEDM Tech. Dig., 2.2.1–2.2.4, 2010.