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Strain-Engineered MOSFETs
3.11 Summary
A brief and comprehensive review on the methods used to introduce
strain in CMOS transistors, such as process-introduced uniaxial strain,
is presented. The semiconductor industry has adopted uniaxial strain
over biaxial strain because of higher performance improvement. Starting
with the 90 nm technology node, uniaxial stress has successfully been
integrated into the mainstream MOSFET process flow. Encouraged by
the strain-enhanced planar MOSFETs, now application of uniaxial stress
to multigate devices is being contemplated with metal gate and high-k
dielectric as a performance booster. However, the drawbacks of uniaxial
stress, e.g., the localised stress dependence on device size and defects
from additional processes, may affect the overall performance and must
be addressed carefully. Some new techniques to introduce stress, such as
the stress memorisation technique and the stress proximity technique, are
also discussed. Uniaxial stress is found to have several advantages over
biaxial stress. Key challenge for integrating stress in CMOS manufacturing technologies is discussed.
Review Questions
1. What is process-induced strain?
2. Discuss the influence of Ge content on stress developed in the channel region.
3. What are the traditional scaling limiters and their implications on
nanoscale MOSFETs?
4. What is the purpose of embedded SiGe in the source/drain region of
a p-MOSFET?
5. Discuss the influence of Ge content on stress developed in the channel region.
6. What is role of graded Ge content in the buffer layer for producing
strained Si films?
7. Compare the local and global strains.
8. What is hybrid orientation technology?
9. How is uniaxial process-induced strain used to enhance mobility?
10. Why is low field mobility important for nanoscale transistors?
Strain-Engineered MOSFETs
3.11 Summary
A brief and comprehensive review on the methods used to introduce
strain in CMOS transistors, such as process-introduced uniaxial strain,
is presented. The semiconductor industry has adopted uniaxial strain
over biaxial strain because of higher performance improvement. Starting
with the 90 nm technology node, uniaxial stress has successfully been
integrated into the mainstream MOSFET process flow. Encouraged by
the strain-enhanced planar MOSFETs, now application of uniaxial stress
to multigate devices is being contemplated with metal gate and high-k
dielectric as a performance booster. However, the drawbacks of uniaxial
stress, e.g., the localised stress dependence on device size and defects
from additional processes, may affect the overall performance and must
be addressed carefully. Some new techniques to introduce stress, such as
the stress memorisation technique and the stress proximity technique, are
also discussed. Uniaxial stress is found to have several advantages over
biaxial stress. Key challenge for integrating stress in CMOS manufacturing technologies is discussed.
Review Questions
1. What is process-induced strain?
2. Discuss the influence of Ge content on stress developed in the channel region.
3. What are the traditional scaling limiters and their implications on
nanoscale MOSFETs?
4. What is the purpose of embedded SiGe in the source/drain region of
a p-MOSFET?
5. Discuss the influence of Ge content on stress developed in the channel region.
6. What is role of graded Ge content in the buffer layer for producing
strained Si films?
7. Compare the local and global strains.
8. What is hybrid orientation technology?
9. How is uniaxial process-induced strain used to enhance mobility?
10. Why is low field mobility important for nanoscale transistors?