83
Process-Induced Stress Engineering in CMOS Technology
1600
1400
1200
1000
Df = 10 µm
Df = 20 µm
Df = 30 µm
KOZ = A* D f
2
800
600
KOZ (µm
2
)
400
200
0
0
5
10
15
D r (µm)
Effect of TSV Diameter D f : KOZ for p-MOS // [110]
20
25
30
35
1000
800
H = 20 µm
H = 50 µm
H = 100 µm
H = 200 µm
600
KOZ (µm
2
)
400
200
0
0
2
4
TSV Aspect Ratio H/D f
Effect of Wafer ickness H: KOZ for p-MOS // [110]
6
8
10
12
FIGURE 3.21
(a) Effect of TSV diameter on KOZ for p-MOSFETs along [110] crystal direction. (b) Effect of
wafer thickness on KOZ for p-MOSFETs along [110] crystal direction (D f = 20 μm, ΔT = −180°C).
(After Lu, K. H., Thermo-Mechanical Reliability of 3-D Interconnects Containing ThroughSilicon-Vias (TSVs), PhD thesis, University of Texas at Austin, 2010.)
Process-Induced Stress Engineering in CMOS Technology
1600
1400
1200
1000
Df = 10 µm
Df = 20 µm
Df = 30 µm
KOZ = A* D f
2
800
600
KOZ (µm
2
)
400
200
0
0
5
10
15
D r (µm)
Effect of TSV Diameter D f : KOZ for p-MOS // [110]
20
25
30
35
1000
800
H = 20 µm
H = 50 µm
H = 100 µm
H = 200 µm
600
KOZ (µm
2
)
400
200
0
0
2
4
TSV Aspect Ratio H/D f
Effect of Wafer ickness H: KOZ for p-MOS // [110]
6
8
10
12
FIGURE 3.21
(a) Effect of TSV diameter on KOZ for p-MOSFETs along [110] crystal direction. (b) Effect of
wafer thickness on KOZ for p-MOSFETs along [110] crystal direction (D f = 20 μm, ΔT = −180°C).
(After Lu, K. H., Thermo-Mechanical Reliability of 3-D Interconnects Containing ThroughSilicon-Vias (TSVs), PhD thesis, University of Texas at Austin, 2010.)