79
Process-Induced Stress Engineering in CMOS Technology
simulations are carried out to calculate the area of KOZ surrounding TSVs.
The area of KOZ has been found to be mainly determined by the channel
direction of the transistor as a result of anisotropic piezoresistivity effects.
Both finite element analysis and analytical models have been proposed to
characterise stress induced by TSVs. The analytical 2D radial stress model
was employed to address the TSV thermomechanical stress effect on device
performance [19]. Tanaka et al. [24] reported that MOS transistor operation after both the postprocessing of TSVs and postassembly was slightly
affected by mechanical stress depending on the distance from a TSV to a
MOS transistor.
Mercha et al. [25] have experimentally demonstrated a significant impact
of TSVs on the adjacent transistors, with up to 30% I dsat shift due to TSV
stress. A FEM model has been proposed using the measured TSV Cu properties (CTE, stress in Cu as a function of temperature, plastic behaviour,
etc.) and relevant information, such as processing temperature profiles,
and was used to predict the mechanical stress tensor throughout the silicon die. Excellent modelling accuracy has been achieved within 0.5% of
the measured I dsat values. The keep-out zones (KOZs) for a large matrix of
TSVs are over 200 μm for analogue circuits and 20 μm for digital circuits. It
has been shown that the complex interaction of stress components makes
it difficult to use simple design rules without sacrificing large layout area.
Numerical 3D stress analysis can be used to accurately estimate KOZ for
different TSV placements.
Low capacitance and resistance and high-density integration are the main
desired features in a TSV structure. Both the required area and interconnect performance heavily rely on TSV process and structures, including the
design of the metal radius, the thickness of the barrier layer, and the doping concentration in the silicon substrate. Figure 3.17(a) shows the impact of
copper radius on threshold voltage, resistance, and the smallest capacitance.
As the radius of copper (r TSV ) increases, the resistance decreases because of
the larger copper cross section, but the capacitance increases. Moreover, the
threshold voltage drops because capacitance increases with the radius of
copper. The trade-offs between the RC delay and the area requirement are
shown for various copper radiuses in Figure 3.17(b). RC product decreases
as a larger copper radius is introduced, implying the impact of resistance
reduction is stronger than the increasing capacitance. On the other hand,
with the growth of copper radius, a larger TSV area is demanded, showing a
trade-off between area and TSV performance. Figure 3.18 shows the threshold voltage changes with the radius of TSV metal. As the radius increases,
the threshold voltage decreases; as oxide thickness increases, the threshold
voltage increases. For a high-frequency operation, the threshold voltage
should be smaller than the applied voltage, as shown in the highlighted area
in Figure 3.18.
Although the TSV stress is not intentionally applied to impact the device
performance, there is a keep-out zone (KOZ) to keep devices unaffected by
Process-Induced Stress Engineering in CMOS Technology
simulations are carried out to calculate the area of KOZ surrounding TSVs.
The area of KOZ has been found to be mainly determined by the channel
direction of the transistor as a result of anisotropic piezoresistivity effects.
Both finite element analysis and analytical models have been proposed to
characterise stress induced by TSVs. The analytical 2D radial stress model
was employed to address the TSV thermomechanical stress effect on device
performance [19]. Tanaka et al. [24] reported that MOS transistor operation after both the postprocessing of TSVs and postassembly was slightly
affected by mechanical stress depending on the distance from a TSV to a
MOS transistor.
Mercha et al. [25] have experimentally demonstrated a significant impact
of TSVs on the adjacent transistors, with up to 30% I dsat shift due to TSV
stress. A FEM model has been proposed using the measured TSV Cu properties (CTE, stress in Cu as a function of temperature, plastic behaviour,
etc.) and relevant information, such as processing temperature profiles,
and was used to predict the mechanical stress tensor throughout the silicon die. Excellent modelling accuracy has been achieved within 0.5% of
the measured I dsat values. The keep-out zones (KOZs) for a large matrix of
TSVs are over 200 μm for analogue circuits and 20 μm for digital circuits. It
has been shown that the complex interaction of stress components makes
it difficult to use simple design rules without sacrificing large layout area.
Numerical 3D stress analysis can be used to accurately estimate KOZ for
different TSV placements.
Low capacitance and resistance and high-density integration are the main
desired features in a TSV structure. Both the required area and interconnect performance heavily rely on TSV process and structures, including the
design of the metal radius, the thickness of the barrier layer, and the doping concentration in the silicon substrate. Figure 3.17(a) shows the impact of
copper radius on threshold voltage, resistance, and the smallest capacitance.
As the radius of copper (r TSV ) increases, the resistance decreases because of
the larger copper cross section, but the capacitance increases. Moreover, the
threshold voltage drops because capacitance increases with the radius of
copper. The trade-offs between the RC delay and the area requirement are
shown for various copper radiuses in Figure 3.17(b). RC product decreases
as a larger copper radius is introduced, implying the impact of resistance
reduction is stronger than the increasing capacitance. On the other hand,
with the growth of copper radius, a larger TSV area is demanded, showing a
trade-off between area and TSV performance. Figure 3.18 shows the threshold voltage changes with the radius of TSV metal. As the radius increases,
the threshold voltage decreases; as oxide thickness increases, the threshold
voltage increases. For a high-frequency operation, the threshold voltage
should be smaller than the applied voltage, as shown in the highlighted area
in Figure 3.18.
Although the TSV stress is not intentionally applied to impact the device
performance, there is a keep-out zone (KOZ) to keep devices unaffected by