78
Strain-Engineered MOSFETs
field in nearby Si. Due to these and other reasons a round TSV geometry was
adopted for TSV test structures.
The through-silicon via (TSV) proximity effect on transistor performance has been reported by Yang et al. [21]. The authors have evaluated
the electrical performance on a 130 nm CMOS platform. In their work,
stacked circuits with TSVs were fabricated on 130 nm CMOS technology
platform. MOSFETs, with TSV proximity in several patterns, were electrically evaluated to detect the possible impact. The TSVs are placed close to
the channel regions of the MOSFETs. The distance between the edge of a
TSV and the edge of a transistor channel was set as 1.1 μm to avoid damaging the device. Designs with multiple TSVs close to a transistor have been
investigated as well.
3.10 TSV Modelling
Modelling of TSV is currently an active research area. Thermomechanical
reliability in 3D interconnects containing TSVs is of serious concern
and includes (1) a thermal stress measurement, (2) TSV-induced thermal
stresses in a Si matrix and the impact on electrical performance of devices,
and (3) TSV-induced thermal stresses at the TSV/Si interface. TSV-induced
stresses in Si are calculated combining analytical solutions and FEA simulations. A 3D semianalytical stress model valid for high-aspect-ratio TSVs
has also been developed [22] to characterise the near-surface stress distribution. The reliability issues, such as carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions
between TSVs induced by the thermal stresses, have been studied by several research groups [23]. A stress model has been developed to model
TSV-induced stress effect to predict the influence of the stress and help
designers optimise the circuit performance. Stress levels calculated via
finite element analysis have shown stress levels can reach the order of several hundred MPa. In this regime, the fractional change in carrier mobility,
Δμ/μ, can be found by the piezoresistance constants of Si. A 100 MPa stress
can induce up to 7% mobility change in Si. Therefore, it will be important
to understand the thermally induced stress development throughout the
process flow to determine keep-out zones that will determine minimum
distances between TSVs and nearby MOSFETs for maintaining acceptable mobility deviations. Interfacial delamination of TSVs was found to
be mainly driven by a shear stress concentration at the TSV/Si interface.
Change in mobility due to TSV stress in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a
high-mobility change is defined as the keep-out zone (KOZ) for transistors.
KOZ is mainly controlled by the TSV geometry and the materials used. FEA
Strain-Engineered MOSFETs
field in nearby Si. Due to these and other reasons a round TSV geometry was
adopted for TSV test structures.
The through-silicon via (TSV) proximity effect on transistor performance has been reported by Yang et al. [21]. The authors have evaluated
the electrical performance on a 130 nm CMOS platform. In their work,
stacked circuits with TSVs were fabricated on 130 nm CMOS technology
platform. MOSFETs, with TSV proximity in several patterns, were electrically evaluated to detect the possible impact. The TSVs are placed close to
the channel regions of the MOSFETs. The distance between the edge of a
TSV and the edge of a transistor channel was set as 1.1 μm to avoid damaging the device. Designs with multiple TSVs close to a transistor have been
investigated as well.
3.10 TSV Modelling
Modelling of TSV is currently an active research area. Thermomechanical
reliability in 3D interconnects containing TSVs is of serious concern
and includes (1) a thermal stress measurement, (2) TSV-induced thermal
stresses in a Si matrix and the impact on electrical performance of devices,
and (3) TSV-induced thermal stresses at the TSV/Si interface. TSV-induced
stresses in Si are calculated combining analytical solutions and FEA simulations. A 3D semianalytical stress model valid for high-aspect-ratio TSVs
has also been developed [22] to characterise the near-surface stress distribution. The reliability issues, such as carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions
between TSVs induced by the thermal stresses, have been studied by several research groups [23]. A stress model has been developed to model
TSV-induced stress effect to predict the influence of the stress and help
designers optimise the circuit performance. Stress levels calculated via
finite element analysis have shown stress levels can reach the order of several hundred MPa. In this regime, the fractional change in carrier mobility,
Δμ/μ, can be found by the piezoresistance constants of Si. A 100 MPa stress
can induce up to 7% mobility change in Si. Therefore, it will be important
to understand the thermally induced stress development throughout the
process flow to determine keep-out zones that will determine minimum
distances between TSVs and nearby MOSFETs for maintaining acceptable mobility deviations. Interfacial delamination of TSVs was found to
be mainly driven by a shear stress concentration at the TSV/Si interface.
Change in mobility due to TSV stress in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a
high-mobility change is defined as the keep-out zone (KOZ) for transistors.
KOZ is mainly controlled by the TSV geometry and the materials used. FEA