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13 Fiber Optic Communication Networks
Fig. 13.34 Timing diagram for the progression of a control packet and a burst through an OBS
network
segment will use to carry the burst. This reservation for the arriving burst is called
burst scheduling.
Figure 13.34 shows an example of a timing diagram for the connection setup
through two intermediate burst switches from source node A to destination node B.
This figure shows that following the transmission of the control packet, the burst
itself is sent after a specified delay called an offset time. The time it takes to set up
a connection depends on the end-to-end propagation time of the control packet, the
sum of all the processing delays t proc of the control packet at intermediate nodes, and
the time t conf it takes to configure the link. Once the link is configured, the travel time
for the burst to reach the destination node is equal to the propagation time, because
no further processing is required for the burst at any intermediate node. Therefore,
the start of the burst has to be delayed by an offset time following transmission of
the control packet in order to give the link enough time to be configured. If there are
N intermediate nodes in the link, then the offset time must be at least Nt proc + t conf .
Note that the edge router sends the burst immediately after expiration of the offset
time without waiting for an acknowledgment from the destination to indicate that
the link is complete. Furthermore, the burst transmission may start before the control
packet reaches its destination.
Solutions for burst-assembly algorithms include formatting a burst based on a
fixed assembly time, a fixed burst length, or a hybrid time-length/burst-length method.
The main parameters are a maximum assembly time threshold T, a maximum burst
length B, and a minimum burst length B min . When the incoming packet flow is low,
the threshold T time ensures that a packet is not delayed too long in the assembly
queue. When the incoming packet flow is high, the upper limit B on the burst size
also limits packet delay times by restricting the time needed to assemble a burst.
Otherwise, if the burst size is not limited, long assembly times could result during
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