24.5 MOSFETs
727
Fig. 24.36 Cross-section
TEM image of 45 nm node
PMOS transistor with
high-k Hf-containing gate
oxide (dark) above a thin
SiO 2 layer (white). The role
of the stressor SiGe pockets
is explained in Fig. 24.35.
Adapted from [2081]
limits (and the effects in nanostructures in the few-nm regime) will be reached beyond 2010, projected
at about 2020. Up to then, it is probable that at least a few companies will follow the road map for
further miniaturization, as laid out by the Semiconductor Industry Association
11 (SIA).
24.5.6 Tunneling FETs
A decisive parameter for FET performance is low leakage current. With shrinking device dimensions
it increases rapidly for conventional FET design. A novel type of FET has thus been conceptualized,
the tunneling FET (TFET) [2088]. It is a lateral p-i-n diode with a MOS gate (Fig. 24.38). The leakage
current is minimized due to the reverse biased p-i-n structure. A low leakage current (per gate width)
of less than 10
−14 A/µm has been realized [2089, 2090]. The channel current is due to band-to-band
tunneling as in an Esaki diode (Sect. 21.5.9) and can be controlled by the gate voltage [2091]. The
surface tunneling junction is close to the source electrode. The use of germanium instead of silicon
allows further performance enhancements [2092].
24.5.7 Nonvolatile Memories
Floating Gate Memories
When the gate electrode of a MOSFET is modified in such a way that a (semi-)
permanent charge can be stored in the gate, a nonvolatile electronic memory can be fabricated. In
the floating-gate structure (Fig. 24.39a), an insulator–metal–insulator structure is used where charge
is stored in the metal and cannot escape through the insulating barriers. The ‘metal’ is often realized
by poly-Si. In the MIOS structure (Fig. 24.39b), the insulator–oxide interface is charged. The charge
can be removed by UV light (EPROM, erasable programmable read-only memory) or by a sufficient
voltage across the oxide at which the charge carriers can tunnel out (Fowler–Nordheim tunneling)
(EEPROM, E
2 PROM, electrically erasable programmable read-only memory).
Nowadays, a special type of EEPROM is used for the so-called flash memories. The stored gate
charge causes a change in the MOSFET threshold voltage and is designed to switch between the on
11 www.semichips.org.
727
Fig. 24.36 Cross-section
TEM image of 45 nm node
PMOS transistor with
high-k Hf-containing gate
oxide (dark) above a thin
SiO 2 layer (white). The role
of the stressor SiGe pockets
is explained in Fig. 24.35.
Adapted from [2081]
limits (and the effects in nanostructures in the few-nm regime) will be reached beyond 2010, projected
at about 2020. Up to then, it is probable that at least a few companies will follow the road map for
further miniaturization, as laid out by the Semiconductor Industry Association
11 (SIA).
24.5.6 Tunneling FETs
A decisive parameter for FET performance is low leakage current. With shrinking device dimensions
it increases rapidly for conventional FET design. A novel type of FET has thus been conceptualized,
the tunneling FET (TFET) [2088]. It is a lateral p-i-n diode with a MOS gate (Fig. 24.38). The leakage
current is minimized due to the reverse biased p-i-n structure. A low leakage current (per gate width)
of less than 10
−14 A/µm has been realized [2089, 2090]. The channel current is due to band-to-band
tunneling as in an Esaki diode (Sect. 21.5.9) and can be controlled by the gate voltage [2091]. The
surface tunneling junction is close to the source electrode. The use of germanium instead of silicon
allows further performance enhancements [2092].
24.5.7 Nonvolatile Memories
Floating Gate Memories
When the gate electrode of a MOSFET is modified in such a way that a (semi-)
permanent charge can be stored in the gate, a nonvolatile electronic memory can be fabricated. In
the floating-gate structure (Fig. 24.39a), an insulator–metal–insulator structure is used where charge
is stored in the metal and cannot escape through the insulating barriers. The ‘metal’ is often realized
by poly-Si. In the MIOS structure (Fig. 24.39b), the insulator–oxide interface is charged. The charge
can be removed by UV light (EPROM, erasable programmable read-only memory) or by a sufficient
voltage across the oxide at which the charge carriers can tunnel out (Fowler–Nordheim tunneling)
(EEPROM, E
2 PROM, electrically erasable programmable read-only memory).
Nowadays, a special type of EEPROM is used for the so-called flash memories. The stored gate
charge causes a change in the MOSFET threshold voltage and is designed to switch between the on
11 www.semichips.org.