726
24 Transistors
The power consumption in active mode P ac depends also on the clock speed (frequency f ) that
increases with higher integration due to shorter gate length,
P ac = C sw V
2
DD f ,
(24.84)
where C sw is the total node capacitance being charged and decharged in a clock cycle.
Historically the oxide thickness has been reduced less than the channel length [2075] (Fig. 24.35a)
leading to increased local fields. The reduction of the physical gate oxide thickness is limited due to gate
leakage through tunneling [2077]. While for a gate voltage of 1.5 V and oxide thickness t ox = 3.6 nm
the leakage current is only about 10
−8 A/cm
2 , it is about 1 A/cm
2 for t ox = 2.0 nm and about 10
4 A/cm
2
for t ox = 1.0 nm. Obviously variations of oxide thickness are more harmful at small average thickness.
1.2 nm physical SiO 2 thickness has been used in the 90 nm (gate length) logic node.
The technological solution for further reduction of oxide thickness is the use of geometrically thicker
layers, to suppress tunneling, with higher dielectric constant (‘high-k dielectrics’), e.g. HfO 2 [2078],
to maintain reasonable gate capacitance per gate width
C G =
ox
t ox
L ,
(24.85)
(cmp. (24.71)) at a value of about 1.0–1.5 fF/µm (Fig. 24.35)b. For the 45 nm technology node a 0.7fold reduction in electrical oxide thickness was achieved while reducing gate leakage 1000× for the
PMOS and 25× for the NMOS transistors [2079].
Materials
The electronics industry is based on silicon as the material for transistors. However, many other
materials are incorporated in the technology. Traditionally silicon dioxide gate oxide is used, silicon
nitride for insulation layers and polysilicon for gate contacts. For wiring aluminum has been used.
Silicides were introduced as contact materials around 1986.
Progress was made with copper interconnects (IBM, 1997), replacing aluminum. The better electrical and heat conductivity could previously not be used since Cu is a deep level in Si (cf. Fig. 7.6). The
key to success was an improved barrier technology based on amorphous TaN- or TiN-based barrier
layers to prevent the diffusion of Cu into the silicon and dielectric layers. The first chip from series
production, incorporating the Cu technology, was the PowerPC 750 (400 MHz) in 1998. Since 2000
high-k, i.e. large r , Hf-containing gate dielectrics are used (Fig. 24.36). HfO 2 has a dielectric constant
of 25–30. 45 nm node technology probably uses HfZrO, HfSiO or HfSiON [2080] gate dielectrics with
k ∼ 12 and an electrical thickness of t ox SiO 2 / ox = 1.0 nm.
Germanium is reintroduced into mainstream semiconductor technology via SiGe stressors in the
source and drain for PMOS. Uniaxial compressive strain in the channel region leads to 30% increased
saturation current [2082] mostly due to reduced effective masses [749, 2083, 2084] (Sect. 8.3.14)
for 90 nm transistors. Similarly, uniaxial tensile strain in NMOS, introduced by SiN caps or more
recently tensile trench contacts [2079], allows for 10% higher saturation current [2082] (Fig. 24.37).
The enhanced electron mobility is due to strain-induced splitting of the X-valley and change of electron
mass [2085]. Further improvement to 18% (NMOS) and 50% (PMOS) increase in I D,sat compared to
unstrained Si have been made in 65 nm transistors [2073].
The end of the miniaturization has been theoretically predicted many times and for various feature
sizes. Today, only fundamental limits such as the size of an atom seems to limit circuit design.
10 Such
10 Only commercial profit, rather than testing physical limits, drives the miniaturization. Insufficient economic advantages
or low yield of further chip generations possibly can limit or slow down large-scale integration.
24 Transistors
The power consumption in active mode P ac depends also on the clock speed (frequency f ) that
increases with higher integration due to shorter gate length,
P ac = C sw V
2
DD f ,
(24.84)
where C sw is the total node capacitance being charged and decharged in a clock cycle.
Historically the oxide thickness has been reduced less than the channel length [2075] (Fig. 24.35a)
leading to increased local fields. The reduction of the physical gate oxide thickness is limited due to gate
leakage through tunneling [2077]. While for a gate voltage of 1.5 V and oxide thickness t ox = 3.6 nm
the leakage current is only about 10
−8 A/cm
2 , it is about 1 A/cm
2 for t ox = 2.0 nm and about 10
4 A/cm
2
for t ox = 1.0 nm. Obviously variations of oxide thickness are more harmful at small average thickness.
1.2 nm physical SiO 2 thickness has been used in the 90 nm (gate length) logic node.
The technological solution for further reduction of oxide thickness is the use of geometrically thicker
layers, to suppress tunneling, with higher dielectric constant (‘high-k dielectrics’), e.g. HfO 2 [2078],
to maintain reasonable gate capacitance per gate width
C G =
ox
t ox
L ,
(24.85)
(cmp. (24.71)) at a value of about 1.0–1.5 fF/µm (Fig. 24.35)b. For the 45 nm technology node a 0.7fold reduction in electrical oxide thickness was achieved while reducing gate leakage 1000× for the
PMOS and 25× for the NMOS transistors [2079].
Materials
The electronics industry is based on silicon as the material for transistors. However, many other
materials are incorporated in the technology. Traditionally silicon dioxide gate oxide is used, silicon
nitride for insulation layers and polysilicon for gate contacts. For wiring aluminum has been used.
Silicides were introduced as contact materials around 1986.
Progress was made with copper interconnects (IBM, 1997), replacing aluminum. The better electrical and heat conductivity could previously not be used since Cu is a deep level in Si (cf. Fig. 7.6). The
key to success was an improved barrier technology based on amorphous TaN- or TiN-based barrier
layers to prevent the diffusion of Cu into the silicon and dielectric layers. The first chip from series
production, incorporating the Cu technology, was the PowerPC 750 (400 MHz) in 1998. Since 2000
high-k, i.e. large r , Hf-containing gate dielectrics are used (Fig. 24.36). HfO 2 has a dielectric constant
of 25–30. 45 nm node technology probably uses HfZrO, HfSiO or HfSiON [2080] gate dielectrics with
k ∼ 12 and an electrical thickness of t ox SiO 2 / ox = 1.0 nm.
Germanium is reintroduced into mainstream semiconductor technology via SiGe stressors in the
source and drain for PMOS. Uniaxial compressive strain in the channel region leads to 30% increased
saturation current [2082] mostly due to reduced effective masses [749, 2083, 2084] (Sect. 8.3.14)
for 90 nm transistors. Similarly, uniaxial tensile strain in NMOS, introduced by SiN caps or more
recently tensile trench contacts [2079], allows for 10% higher saturation current [2082] (Fig. 24.37).
The enhanced electron mobility is due to strain-induced splitting of the X-valley and change of electron
mass [2085]. Further improvement to 18% (NMOS) and 50% (PMOS) increase in I D,sat compared to
unstrained Si have been made in 65 nm transistors [2073].
The end of the miniaturization has been theoretically predicted many times and for various feature
sizes. Today, only fundamental limits such as the size of an atom seems to limit circuit design.
10 Such
10 Only commercial profit, rather than testing physical limits, drives the miniaturization. Insufficient economic advantages
or low yield of further chip generations possibly can limit or slow down large-scale integration.