24.5 MOSFETs
725
(a)
(b)
Fig. 24.35 Scaling of MOSFET parameters gate oxide thickness t ox , power supply voltage V DD (across source–drain),
threshold voltage V T , total power loss per area P, gate capacitance per channel width C G and inverter delay τ , the time
required to propagate a transition through a single inverter driving a second, identical inverter, commonly used as a
means of gauging the speed of CMOS transistors. Data for a from [2075] and for b selected from [2076]
The increase of the number of transistors per area requires the scaling of their geometrical properties.
This impacts many other properties of the transistor and their scaling needs to be considered as well.
From a general perspective, the physical properties scale while the thermal energy kT remains constant
for room-temperature electronics.
If channel width Z and channel length L of a transistor are scaled down by a factor of s > 1,
Z
= Z /s and L
= L/s, the area obviously scales as A
= A/s
2 . In subsequent transistor generations
s =
√
2, i.e. doubling of the number of devices per area. In order to maintain the aspect ratio of the
device also the oxide thickness (d i ) is scaled, t
ox = t ox /s (‘classical scaling’).
The ultimate design criteria are maximum temperature and maximum power loss. The maximum
temperature needs to be obeyed, the worst case usually taken as 100
◦ C. The power loss per area, e.g.
heating, needs to stay constant at an appropriate maximum level around 200 kW/m
2 (Fig. 24.35b) unless
higher (and more expensive) efforts on cooling are made. At the same time the device performance
needs to be maintained if not improved, e.g. for lower power dissipation in battery operated devices.
Very important is the reduction of operation voltage V DD in order to keep electric fields and power
consumption small enough (Fig. 24.35). The power consumption in stand-by mode P off depends on
V DD and the subthreshold (off) current
P off = W tot V DD I off ,
(24.82)
where W tot is the total width of the turned-off devices and I off is the average off-current per device per
width. The latter increases exponentially with reduced threshold voltage V T ,
I off = I 0 exp
−
e V T
n kT
,
(24.83)
with ideality factor n ≈ 1.2 and I 0 ≈ 1–10 µA/µm [2075]. A well-functioning MOSFET requires a
ratio of V T /V DD of < 0.3.
725
(a)
(b)
Fig. 24.35 Scaling of MOSFET parameters gate oxide thickness t ox , power supply voltage V DD (across source–drain),
threshold voltage V T , total power loss per area P, gate capacitance per channel width C G and inverter delay τ , the time
required to propagate a transition through a single inverter driving a second, identical inverter, commonly used as a
means of gauging the speed of CMOS transistors. Data for a from [2075] and for b selected from [2076]
The increase of the number of transistors per area requires the scaling of their geometrical properties.
This impacts many other properties of the transistor and their scaling needs to be considered as well.
From a general perspective, the physical properties scale while the thermal energy kT remains constant
for room-temperature electronics.
If channel width Z and channel length L of a transistor are scaled down by a factor of s > 1,
Z
= Z /s and L
= L/s, the area obviously scales as A
= A/s
2 . In subsequent transistor generations
s =
√
2, i.e. doubling of the number of devices per area. In order to maintain the aspect ratio of the
device also the oxide thickness (d i ) is scaled, t
ox = t ox /s (‘classical scaling’).
The ultimate design criteria are maximum temperature and maximum power loss. The maximum
temperature needs to be obeyed, the worst case usually taken as 100
◦ C. The power loss per area, e.g.
heating, needs to stay constant at an appropriate maximum level around 200 kW/m
2 (Fig. 24.35b) unless
higher (and more expensive) efforts on cooling are made. At the same time the device performance
needs to be maintained if not improved, e.g. for lower power dissipation in battery operated devices.
Very important is the reduction of operation voltage V DD in order to keep electric fields and power
consumption small enough (Fig. 24.35). The power consumption in stand-by mode P off depends on
V DD and the subthreshold (off) current
P off = W tot V DD I off ,
(24.82)
where W tot is the total width of the turned-off devices and I off is the average off-current per device per
width. The latter increases exponentially with reduced threshold voltage V T ,
I off = I 0 exp
−
e V T
n kT
,
(24.83)
with ideality factor n ≈ 1.2 and I 0 ≈ 1–10 µA/µm [2075]. A well-functioning MOSFET requires a
ratio of V T /V DD of < 0.3.