724
24 Transistors
Fig. 24.32 Resistivity of
copper at room temperature
for various film thickness
(solid circles), and for a
100 nm-film as a function
of line width w (empty
circles). Solid lines are
theoretical dependence
according to (24.81). The
dashed lines indicate the
limits for bulk material
(t → ∞) and for large line
thickness (d = 100 nm,
w → ∞). Adapted
from [2071]
Fig. 24.33 Cross section through a logic chip (65 nm technology, 35 nm gate length) with eight layers of dual damascene
Cu interconnects (M1–M8) with low-k carbon-doped oxide ( r = 2.9) inter-level dielectric above the active elements.
Adapted from [2073]
Fig. 24.34 Plane-view of the first three interconnect layers of a 45 nm node SRAM array (Intel ® Xeon ® ). In the image of
the M1 layer the gate layer metal connects are shown in the inset, framed with a white dashed line. Adapted from [2074]