24.5 MOSFETs
723
(a)
(b)
Fig. 24.31 a Moore’s law on the exponential increase of transistors per chip (for Intel TM processor chips). Dashed line
corresponds to doubling in 20 months. b Historical increase of maximum clock speed, dashed line is guide to the eye.
Note the almost constant rate of 10 MHz from the mid-1970s to the mid-1980s and another plateau developing after 2000
Interconnects
Moore’s second law says that the cost of production also doubles for each new chip generation and
is currently (2004) in the multi-billion US$ range. Most of the cost saved by integration is due to
efficient wiring (interconnects) of the components, in 2004 (65 nm node) in eight layers above the
active elements (transistors and capacitors) (Fig. 24.33), in 2008 (45 nm node) in eleven layers. Planeview images of the first three layers of the interconnects are shown in Fig. 24.34. The Cu interconnects
are fabricated with the so-called damascene process [2068–2070]. Barrier layers (e.g. TaN or TiN) are
required to avoid out-diffusion of Cu into the silicon or other parts of the circuit. Three effects limit the
conductivity: The interconnect metal line width and height approaches the mean free path of carriers
(d Cu ≈ 40 nm) [715, 2071], grain boundary scattering can limit mobility since grain size is reduced for
thinner lines, and the (high resistivity) barrier reduces space for the conductive part of the metal line.
In Fig. 24.32 the increase of the resistivity of copper with reduced dimension is shown as a function
of film thickness t and for a 100 nm-film as a function of line width w. In a simplified approach, the
line resistivity ρ line is given as [2071]
ρ line
ρ 0
= 1 +
3
8
(1 − p)
d
t
+
d
w
,
(24.81)
ρ 0 denoting the bulk resistivity (1.7 µ cm for Cu), d being the mean free path (8.7) and p being the
electron scattering parameter ( p = 0 for diffuse scattering).
In order to achieve the best high frequency performance the material between the metal interconnects
should have low dielectric constant (‘low-k’ dielectric). Alternative materials to the standard SiO 2
( r ≈ 4.1) are investigated such as SiOF (≈ 3.8), SiCOH (≈ 3.0), porous materials (≈ 2.5) and air
gaps [2072].
CMOS Scaling
Using planar technologies, LSI (large-scale integration), VLSI (very large-scale integration), ULSI
(ultra large-scale integration) and further generations of devices have been conceived, driven by highdensity electronic memory devices. Subsequently also logic devices are produced with reduced device
size.
723
(a)
(b)
Fig. 24.31 a Moore’s law on the exponential increase of transistors per chip (for Intel TM processor chips). Dashed line
corresponds to doubling in 20 months. b Historical increase of maximum clock speed, dashed line is guide to the eye.
Note the almost constant rate of 10 MHz from the mid-1970s to the mid-1980s and another plateau developing after 2000
Interconnects
Moore’s second law says that the cost of production also doubles for each new chip generation and
is currently (2004) in the multi-billion US$ range. Most of the cost saved by integration is due to
efficient wiring (interconnects) of the components, in 2004 (65 nm node) in eight layers above the
active elements (transistors and capacitors) (Fig. 24.33), in 2008 (45 nm node) in eleven layers. Planeview images of the first three layers of the interconnects are shown in Fig. 24.34. The Cu interconnects
are fabricated with the so-called damascene process [2068–2070]. Barrier layers (e.g. TaN or TiN) are
required to avoid out-diffusion of Cu into the silicon or other parts of the circuit. Three effects limit the
conductivity: The interconnect metal line width and height approaches the mean free path of carriers
(d Cu ≈ 40 nm) [715, 2071], grain boundary scattering can limit mobility since grain size is reduced for
thinner lines, and the (high resistivity) barrier reduces space for the conductive part of the metal line.
In Fig. 24.32 the increase of the resistivity of copper with reduced dimension is shown as a function
of film thickness t and for a 100 nm-film as a function of line width w. In a simplified approach, the
line resistivity ρ line is given as [2071]
ρ line
ρ 0
= 1 +
3
8
(1 − p)
d
t
+
d
w
,
(24.81)
ρ 0 denoting the bulk resistivity (1.7 µ cm for Cu), d being the mean free path (8.7) and p being the
electron scattering parameter ( p = 0 for diffuse scattering).
In order to achieve the best high frequency performance the material between the metal interconnects
should have low dielectric constant (‘low-k’ dielectric). Alternative materials to the standard SiO 2
( r ≈ 4.1) are investigated such as SiOF (≈ 3.8), SiCOH (≈ 3.0), porous materials (≈ 2.5) and air
gaps [2072].
CMOS Scaling
Using planar technologies, LSI (large-scale integration), VLSI (very large-scale integration), ULSI
(ultra large-scale integration) and further generations of devices have been conceived, driven by highdensity electronic memory devices. Subsequently also logic devices are produced with reduced device
size.