24.5 MOSFETs
719
capacitor flows over the NMOS to ground. The PMOS transistor has zero gate–source voltage and is
in the ‘off’ state. In this case, the voltage V DD drops entirely across the PMOS and the capacitor is
uncharged with V out = 0.
In both its logic states, the CMOS inverter does not consume power. No current
7 flows in either of
the two steady states since one of the two transistors is in both cases in the ‘off’ state. Current flows
only during the switching operation. Therefore, the CMOS scheme allows for low power consumption.
The middle voltage for which V in = V out can be calculated from the MOSFET characteristics. Both
are, for this condition, in saturation and the currents are given by (cf. (24.70))
I Dn = μ n C ox
Z n
2L n
(V M − V Tn )
2
(24.79a)
I Dp = μ p C ox
Z p
2L p
V DD − V M − V Tp
2 .
(24.79b)
With γ =
Z p
Z n
L n
L p
μ p
(−μ n )
, we find from I Dn = −I Dp ,
V M =
V Tn + γ
V DD + V Tp
1 + γ
.
(24.80)
As gate material, often polycrystalline silicon (poly-Si) is used (cf. Fig. 21.29). It is used instead of
metals because its work function matches that of silicon closely. Also, poly-Si is more resistant to
temperature. Despite its high doping, the resistance of poly-Si is two orders of magnitude larger than
that of metals. Since it is easily oxidized, it cannot be used with high-k oxide dielectrics.
8
For optimized ohmic contacts on the n- and p-Si, different metals are used to create a small barrier
height (Fig. 21.23a) and low contact resistance (cf. Sect. 21.2.6). Figure 24.27 visualizes the band edges
of silicon in relation to the work functions of various metals (see Table 21.2). For example, the work
function of titanium matches the electron affinity of n-Si closely. However, a direct deposition of Ti on
Si results in a Schottky barrier of 0.5 eV [1690]. A surface passivation with a group-VI element such
as Se can help reduce this value to 0.19 eV [2065].
Fig. 24.25 The four
MOSFET types. a
Enhancement and b
depletion type with
n-channel (top row) and
p-channel (bottom row)
(a)
S
G
D
n
+
p
n
+
S
G
D
n
+
p
n
+
n-channel
n-channel
(b)
7 except for the subthreshold current and other leakage currents. These need to be reduced further since the dissipated
power limits chip performance (speed and device density) and battery lifetime in handheld applications.
8 The term ‘high-k dielectric’ means a dielectric material with large dielectric constant
719
capacitor flows over the NMOS to ground. The PMOS transistor has zero gate–source voltage and is
in the ‘off’ state. In this case, the voltage V DD drops entirely across the PMOS and the capacitor is
uncharged with V out = 0.
In both its logic states, the CMOS inverter does not consume power. No current
7 flows in either of
the two steady states since one of the two transistors is in both cases in the ‘off’ state. Current flows
only during the switching operation. Therefore, the CMOS scheme allows for low power consumption.
The middle voltage for which V in = V out can be calculated from the MOSFET characteristics. Both
are, for this condition, in saturation and the currents are given by (cf. (24.70))
I Dn = μ n C ox
Z n
2L n
(V M − V Tn )
2
(24.79a)
I Dp = μ p C ox
Z p
2L p
V DD − V M − V Tp
2 .
(24.79b)
With γ =
Z p
Z n
L n
L p
μ p
(−μ n )
, we find from I Dn = −I Dp ,
V M =
V Tn + γ
V DD + V Tp
1 + γ
.
(24.80)
As gate material, often polycrystalline silicon (poly-Si) is used (cf. Fig. 21.29). It is used instead of
metals because its work function matches that of silicon closely. Also, poly-Si is more resistant to
temperature. Despite its high doping, the resistance of poly-Si is two orders of magnitude larger than
that of metals. Since it is easily oxidized, it cannot be used with high-k oxide dielectrics.
8
For optimized ohmic contacts on the n- and p-Si, different metals are used to create a small barrier
height (Fig. 21.23a) and low contact resistance (cf. Sect. 21.2.6). Figure 24.27 visualizes the band edges
of silicon in relation to the work functions of various metals (see Table 21.2). For example, the work
function of titanium matches the electron affinity of n-Si closely. However, a direct deposition of Ti on
Si results in a Schottky barrier of 0.5 eV [1690]. A surface passivation with a group-VI element such
as Se can help reduce this value to 0.19 eV [2065].
Fig. 24.25 The four
MOSFET types. a
Enhancement and b
depletion type with
n-channel (top row) and
p-channel (bottom row)
(a)
S
G
D
n
+
p
n
+
S
G
D
n
+
p
n
+
n-channel
n-channel
(b)
7 except for the subthreshold current and other leakage currents. These need to be reduced further since the dissipated
power limits chip performance (speed and device density) and battery lifetime in handheld applications.
8 The term ‘high-k dielectric’ means a dielectric material with large dielectric constant