720
24 Transistors
In the latest generation of CMOS ICs the PMOS (NMOS) device has a built-in compressive (tensile)
channel strain for modifying the effective mass (cf. Sect. 6.12.2), both allowing higher drive current
due to higher mobility. A detailed treatment can be found in [2066].
(a)
V DD
C L
V in
V out
S
S
G
G
(b)
V DD
C L
V in
V out
S
S
G
G
(c)
(d)
(e)
input
GND
output
VDD
nMOS
n-type
diffusion
p-type
diffusion
n-well
pMOS
p-Si
n+
n+
+
p
+
n
p+
n-well
poly-Si
gate
n-well
contact
source
gate
oxide
drain
source
metal
SiO 2
SiO 2
n-MOSFET
p-MOSFET
Fig. 24.26 Circuit diagram of a inverter with n-type (bottom) and p-type (normally off, enhancement mode) FETs
and b inverter with p-type (bottom) and n-type (normally on, depletion mode) FETs. c Inverter characteristic with the
transistor thresholds indicated, d inverter characteristic with middle voltage V M indicated. NM L,H denotes the low- and
high-noise margins, respectively, i.e. the voltage by which the input voltage can fluctuate without leading to switching.
e Composite layout (left panel) and cross-sectional view (right panel) of CMOS inverter. Part e adapted from [2064]