718
24 Transistors
Fig. 24.24 Experimental
subthreshold I –V
characteristic of a
MOSFET device with long
channel (15.5 µm). Solid
lines for V D = 10 V,
dashed lines for
V D = 0.1 V. Adapted
from [2063]
1
3
2
V (V)
G
10
-3
10
10
10
10
10
10
10
10
-4
-5
-6
-7
-8
-9
-10
-11
I (A)
D
V =0V
BS
3V
10V
V T
V T
V T
V =0.1V
D
V =10V
D
I D = μ n
Z a C i n
2
i
2 L β 2 N
2
A
1 − exp (−βV D )
exp (−β s ) (β s )
−1/2
.
(24.77)
The drain current therefore increases exponentially with V G , as shown in Fig. 24.24. V G is approximately
linear proportional to B :
s = (V G − V FB ) −
a
2
2β
1 +
4
a 2 (βV G − βV FB − 1) − 1
,
(24.78)
where V FB is the flat-band voltage of the gate MIS diode. The drain current is independent of V D for
V D 3kT /e.
24.5.3 MOSFET Types
MOSFETs can have an n-type channel (on a p-substrate) or a p-channel (on an n-type substrate). So
far, we have discussed the normally off MOSFET. If there is a conductive channel even without a
gate voltage, the MOSFET is normally on. Here, a negative gate voltage must be applied to close the
channel. Therefore, similar to the JFET, a total of four different types of MOSFET exist, see Fig. 24.25.
24.5.4 Complementary MOS
Complementary metal–oxide–semiconductor technology (CMOS) is the dominating technology for
highly integrated circuits. In such devices, MOSFETs with n-channel (NMOS) and p-channel (PMOS)
are used on the same chip. The basic structure of logic circuits, the inverter, can be realized with a pair
of NMOS and PMOS transistors, as shown in Fig. 24.26a with two normally off transistors. The load
capacitor represents the capacitance of the following elements.
If the input voltage is V in = 0, the NMOS transistor is nonconductive (‘off’). The (positive) voltage
V DD is at the PMOS transistor source, thus the gate is negative in relation to the source and the transistor
is conductive (‘on’) since −V DD = V Gp < V Tp < 0 (see Fig. 24.25). The current flows through the
capacitor that becomes charged to V out = V DD . The current then subsides, since V D at the PMOS
becomes zero. If the input voltage is set to V DD , the NMOS transistor has a positive gate–source
voltage larger than the threshold V Tn < V Gn = V DD and becomes conductive. The charge from the
24 Transistors
Fig. 24.24 Experimental
subthreshold I –V
characteristic of a
MOSFET device with long
channel (15.5 µm). Solid
lines for V D = 10 V,
dashed lines for
V D = 0.1 V. Adapted
from [2063]
1
3
2
V (V)
G
10
-3
10
10
10
10
10
10
10
10
-4
-5
-6
-7
-8
-9
-10
-11
I (A)
D
V =0V
BS
3V
10V
V T
V T
V T
V =0.1V
D
V =10V
D
I D = μ n
Z a C i n
2
i
2 L β 2 N
2
A
1 − exp (−βV D )
exp (−β s ) (β s )
−1/2
.
(24.77)
The drain current therefore increases exponentially with V G , as shown in Fig. 24.24. V G is approximately
linear proportional to B :
s = (V G − V FB ) −
a
2
2β
1 +
4
a 2 (βV G − βV FB − 1) − 1
,
(24.78)
where V FB is the flat-band voltage of the gate MIS diode. The drain current is independent of V D for
V D 3kT /e.
24.5.3 MOSFET Types
MOSFETs can have an n-type channel (on a p-substrate) or a p-channel (on an n-type substrate). So
far, we have discussed the normally off MOSFET. If there is a conductive channel even without a
gate voltage, the MOSFET is normally on. Here, a negative gate voltage must be applied to close the
channel. Therefore, similar to the JFET, a total of four different types of MOSFET exist, see Fig. 24.25.
24.5.4 Complementary MOS
Complementary metal–oxide–semiconductor technology (CMOS) is the dominating technology for
highly integrated circuits. In such devices, MOSFETs with n-channel (NMOS) and p-channel (PMOS)
are used on the same chip. The basic structure of logic circuits, the inverter, can be realized with a pair
of NMOS and PMOS transistors, as shown in Fig. 24.26a with two normally off transistors. The load
capacitor represents the capacitance of the following elements.
If the input voltage is V in = 0, the NMOS transistor is nonconductive (‘off’). The (positive) voltage
V DD is at the PMOS transistor source, thus the gate is negative in relation to the source and the transistor
is conductive (‘on’) since −V DD = V Gp < V Tp < 0 (see Fig. 24.25). The current flows through the
capacitor that becomes charged to V out = V DD . The current then subsides, since V D at the PMOS
becomes zero. If the input voltage is set to V DD , the NMOS transistor has a positive gate–source
voltage larger than the threshold V Tn < V Gn = V DD and becomes conductive. The charge from the