E1C07 09/14/2010
14:43:49 Page 277
KNOWN 12-bit resolution (see Ex. 7.4)
FIND (u c ) E measured
SOLUTION We can estimate a design-stage uncertainty as a combination of uncertainty due to
quantization errors u Q and due to conversion errors u c :
u d
ð Þ E ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi
u 2
o þ u 2
c
q
The resolution of a 12-bit A/D converter with full-scale range of 0 to 10 V is (see Ex. 7.3) u Q ¼
2.4 mV, so that the quantization error is estimated by the zero-order uncertainty:
u o ¼
1
2
Q ¼ 1:2 mV
Now the conversion error is affected by two elements:
Linearity uncertainty ¼ u 2 ¼ 3 bits  2:4 mV
¼ 7:2 mV
Temperature uncertainty ¼ u 3 ¼
1 bit
5
C
 10
C Â 2:4 mV
¼ 4:8 mV
An estimate of the uncertainty due to conversion errors is found using the RSS method:
u c ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi
u 2
2 þ u 2
3
q
¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
7:2 mV
ð
Þ
2 þ 4:8 mV
ð
Þ
2
q
¼ 8:6 mV
The combined uncertainty in the digital representation of an analog value due to these uncertainties
is an interval described as
u d
ð Þ E ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1:2 mV
ð
Þ
2 þ 8:6 mV
ð
Þ
2
q
¼ Æ8:7 mV 95% assumed
ð
Þ
The effects of the conversion errors dominate the uncertainty.
Successive Approximation Converters
We next discuss several common methods for converting voltage signals into binary words.
Additional methods for A/D conversion are discussed in specialized texts (5,7).
The most common type of A/D converter uses the successive approximation technique. This
technique uses a trial-and-error approach for converting the input voltage. Basically, the successive
approximation A/D converter guesses successive binary values as it narrows in on the appropriate
binary representation for the input voltage. As depicted in Figure 7.8, this A/D converter uses an
M-bit register to generate a trial binary number, a D/A converter to convert the register contents into
an analog voltage, and a voltage comparator (see Section 6.7 in Chapter 6) to compare the input
voltage to the internally generated voltage. The conversion sequence is as follows:
1. The MSB is set to 1. All other bits are set to 0. This produces a value of E
à at the D/A
converter output equivalent to the register setting. If E
Ã
> E i , the comparator goes LOW,
causing the MSB to be reset to 0. If E
Ã
< E i , the MSB is kept HIGH at 1.
7.5 Voltage Measurements 277
14:43:49 Page 277
KNOWN 12-bit resolution (see Ex. 7.4)
FIND (u c ) E measured
SOLUTION We can estimate a design-stage uncertainty as a combination of uncertainty due to
quantization errors u Q and due to conversion errors u c :
u d
ð Þ E ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi
u 2
o þ u 2
c
q
The resolution of a 12-bit A/D converter with full-scale range of 0 to 10 V is (see Ex. 7.3) u Q ¼
2.4 mV, so that the quantization error is estimated by the zero-order uncertainty:
u o ¼
1
2
Q ¼ 1:2 mV
Now the conversion error is affected by two elements:
Linearity uncertainty ¼ u 2 ¼ 3 bits  2:4 mV
¼ 7:2 mV
Temperature uncertainty ¼ u 3 ¼
1 bit
5
C
 10
C Â 2:4 mV
¼ 4:8 mV
An estimate of the uncertainty due to conversion errors is found using the RSS method:
u c ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi
u 2
2 þ u 2
3
q
¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
7:2 mV
ð
Þ
2 þ 4:8 mV
ð
Þ
2
q
¼ 8:6 mV
The combined uncertainty in the digital representation of an analog value due to these uncertainties
is an interval described as
u d
ð Þ E ¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1:2 mV
ð
Þ
2 þ 8:6 mV
ð
Þ
2
q
¼ Æ8:7 mV 95% assumed
ð
Þ
The effects of the conversion errors dominate the uncertainty.
Successive Approximation Converters
We next discuss several common methods for converting voltage signals into binary words.
Additional methods for A/D conversion are discussed in specialized texts (5,7).
The most common type of A/D converter uses the successive approximation technique. This
technique uses a trial-and-error approach for converting the input voltage. Basically, the successive
approximation A/D converter guesses successive binary values as it narrows in on the appropriate
binary representation for the input voltage. As depicted in Figure 7.8, this A/D converter uses an
M-bit register to generate a trial binary number, a D/A converter to convert the register contents into
an analog voltage, and a voltage comparator (see Section 6.7 in Chapter 6) to compare the input
voltage to the internally generated voltage. The conversion sequence is as follows:
1. The MSB is set to 1. All other bits are set to 0. This produces a value of E
à at the D/A
converter output equivalent to the register setting. If E
Ã
> E i , the comparator goes LOW,
causing the MSB to be reset to 0. If E
Ã
< E i , the MSB is kept HIGH at 1.
7.5 Voltage Measurements 277