80
3 SAMPA Chip Implementation
forced to a value if the coupling cell is in a certain state. Only a fraction of these
can reliably be detected with the currently used test algorithm.
Transition faults A cell or line fails to undergo a transition from 0 to 1 or 1 to 0.
Data retention faults When the cell is unable to hold its value. In SRAM this
could be caused by defective pull-ups. Data retention is tested by adding a delay
after the normal sequence is done and then continue after the delay. As the SAMPA
does not rely particularly on a long retention time in the memory, this was not
added in the automatic test. On the other hand, it would be possible to test this by
stopping the clocks to the SAMPA for a while before enabling them again.
Read disturb fault Reading the cell multiple times will flip its content. Multiple
reads on the same cell are not done with the current algorithm.
A more common industry technique is to use a 13N algorithm as with the Inductive
Fault Analysis (IFA) algorithm [18] or a 14N as with March SRD [16] for complete
coverage. Full coverage for the previously mentioned techniques is only valid for
memories with individual cell access. Word-oriented SRAM, where a complete word
is read and written at once, introduces the problem of state coupling faults between
two cells at one address. To detect these faults all four state transitions between two
cells must be tested. This would be done by running the same test with different
patterns. For a 10-bit memory like in the SAMPA, this would require five iterations
of the algorithm [18], significantly increasing test time. Coupling coverage could
have been a bit better if the true physical layout of the cells in a word would have
been known so that the chequerboard pattern is represented in the actual layout.
For using the pulsed output from the device for SEU detection, there are some
considerations;
• Multiple changed bits in the same address are only detected as one error.
• All the memory tests are run in parallel with the error outputs ORed together, so if
two memory testers discover an error at the same time, they will mask each other.
• The pulse length for a found error is one clock cycle of the clock domain the
memory tester is running at. If an error is found in two or more consecutive
addresses, the error signal from those addresses will be conjoined.
All of this will add to the dead time of the system as well as the uncertainty in the
total number of errors found.
A possible extension to the BIST is to make it controllable through the JTAG.
This would provide the possibility to supply different patterns to the tester, which
would cover testing of more coupling faults. By adding some extra complexity, it
would be possible to make the algorithm programmable. The default simple test
would then provide enough detection of faults before packaging, while the extended
testing could be done post-packaging if a higher fault detection was required.
3 SAMPA Chip Implementation
forced to a value if the coupling cell is in a certain state. Only a fraction of these
can reliably be detected with the currently used test algorithm.
Transition faults A cell or line fails to undergo a transition from 0 to 1 or 1 to 0.
Data retention faults When the cell is unable to hold its value. In SRAM this
could be caused by defective pull-ups. Data retention is tested by adding a delay
after the normal sequence is done and then continue after the delay. As the SAMPA
does not rely particularly on a long retention time in the memory, this was not
added in the automatic test. On the other hand, it would be possible to test this by
stopping the clocks to the SAMPA for a while before enabling them again.
Read disturb fault Reading the cell multiple times will flip its content. Multiple
reads on the same cell are not done with the current algorithm.
A more common industry technique is to use a 13N algorithm as with the Inductive
Fault Analysis (IFA) algorithm [18] or a 14N as with March SRD [16] for complete
coverage. Full coverage for the previously mentioned techniques is only valid for
memories with individual cell access. Word-oriented SRAM, where a complete word
is read and written at once, introduces the problem of state coupling faults between
two cells at one address. To detect these faults all four state transitions between two
cells must be tested. This would be done by running the same test with different
patterns. For a 10-bit memory like in the SAMPA, this would require five iterations
of the algorithm [18], significantly increasing test time. Coupling coverage could
have been a bit better if the true physical layout of the cells in a word would have
been known so that the chequerboard pattern is represented in the actual layout.
For using the pulsed output from the device for SEU detection, there are some
considerations;
• Multiple changed bits in the same address are only detected as one error.
• All the memory tests are run in parallel with the error outputs ORed together, so if
two memory testers discover an error at the same time, they will mask each other.
• The pulse length for a found error is one clock cycle of the clock domain the
memory tester is running at. If an error is found in two or more consecutive
addresses, the error signal from those addresses will be conjoined.
All of this will add to the dead time of the system as well as the uncertainty in the
total number of errors found.
A possible extension to the BIST is to make it controllable through the JTAG.
This would provide the possibility to supply different patterns to the tester, which
would cover testing of more coupling faults. By adding some extra complexity, it
would be possible to make the algorithm programmable. The default simple test
would then provide enough detection of faults before packaging, while the extended
testing could be done post-packaging if a higher fault detection was required.