3.3 Design for Test
81
3.3.3 JTAG Boundary Scan
JTAG (IEEE/ANSI Standard 1149.1-2013) [19] defines a standard for adding a dedicated JTAG port to a device for debugging purposes. Internally the device runs a
state machine, which operates independently of the rest of the device and is controllable through the serial interface of the JTAG port. Several devices can be chained
together by connecting the serial data output of one device to the serial data input of
the next. Instructions can be loaded into the device to control the behaviour of the
state machine. The SAMPA supports the minimum required instructions, which are
to sample the input pins, load the output pins and bypass the device.
There can be manufacturing errors at several steps in the production that can lead
to inaccessible or shorted pins. There can be broken or shorted bond wires between
the die and the carrier PCB of the package. There could be manufacturing errors in
the carrier PCB of the package. There can also be bad solder connections between
the package and the front-end card as well as broken traces on the front-end card. The
JTAG provides a quick way to verify that there is a connection between an external
device and the chip internal to the package and that there are no shorts between the
signals. The same is possible with the scan chain capability as well, but the scan chain
test takes longer to complete and will require analysis of the results to determine what
the specific error is.
3.3.4 Ring Oscillator
A ring oscillator circuitry has been implemented to track process variations in the
manufacturing and determine the effect that changes in supply voltage and temperature has on the speed of the digital design. The circuit diagram is shown in Fig. 3.21. It
consists of the inverter ring, a frequency divide-by-16, two counters running respectively on the divide-by-16 ring oscillator clock and a reference 10 MHz clock and
some glue circuitry to control and end the test. The length of the ring was chosen so
that the operating frequency would be 160 MHz in the typical temperature/voltage
corner. Consequently, the frequency in the worst-case corner would be 100 MHz,
and 220 MHz for the best case, based on simulation and available propagation delay
values from the manufacturer’s datasheet. The number of stages is odd to sustain
an oscillation and it is a prime number to reduce the likelihood of higher harmonic
resonances being present [20]. As the enable signal is generated locally on-chip it
will have a rather monotonically increasing sharp edge and have little noise, combined with the relatively low speed of the oscillation there should be little chance
of injecting multiple pulses due to the transitioning of the enable signal from “0” to
“1”.
To be able to automatically determine the frequency of the ring oscillator, the
frequency is divided by 16 and compared against the ADC clock. A counter for each
clock is started at the same time and after the ADC clock counter has run for 255
81
3.3.3 JTAG Boundary Scan
JTAG (IEEE/ANSI Standard 1149.1-2013) [19] defines a standard for adding a dedicated JTAG port to a device for debugging purposes. Internally the device runs a
state machine, which operates independently of the rest of the device and is controllable through the serial interface of the JTAG port. Several devices can be chained
together by connecting the serial data output of one device to the serial data input of
the next. Instructions can be loaded into the device to control the behaviour of the
state machine. The SAMPA supports the minimum required instructions, which are
to sample the input pins, load the output pins and bypass the device.
There can be manufacturing errors at several steps in the production that can lead
to inaccessible or shorted pins. There can be broken or shorted bond wires between
the die and the carrier PCB of the package. There could be manufacturing errors in
the carrier PCB of the package. There can also be bad solder connections between
the package and the front-end card as well as broken traces on the front-end card. The
JTAG provides a quick way to verify that there is a connection between an external
device and the chip internal to the package and that there are no shorts between the
signals. The same is possible with the scan chain capability as well, but the scan chain
test takes longer to complete and will require analysis of the results to determine what
the specific error is.
3.3.4 Ring Oscillator
A ring oscillator circuitry has been implemented to track process variations in the
manufacturing and determine the effect that changes in supply voltage and temperature has on the speed of the digital design. The circuit diagram is shown in Fig. 3.21. It
consists of the inverter ring, a frequency divide-by-16, two counters running respectively on the divide-by-16 ring oscillator clock and a reference 10 MHz clock and
some glue circuitry to control and end the test. The length of the ring was chosen so
that the operating frequency would be 160 MHz in the typical temperature/voltage
corner. Consequently, the frequency in the worst-case corner would be 100 MHz,
and 220 MHz for the best case, based on simulation and available propagation delay
values from the manufacturer’s datasheet. The number of stages is odd to sustain
an oscillation and it is a prime number to reduce the likelihood of higher harmonic
resonances being present [20]. As the enable signal is generated locally on-chip it
will have a rather monotonically increasing sharp edge and have little noise, combined with the relatively low speed of the oscillation there should be little chance
of injecting multiple pulses due to the transitioning of the enable signal from “0” to
“1”.
To be able to automatically determine the frequency of the ring oscillator, the
frequency is divided by 16 and compared against the ADC clock. A counter for each
clock is started at the same time and after the ADC clock counter has run for 255