3.3 Design for Test
79
The algorithm used for testing is a 5N length test (3N for dual port memory),
where N is the number of addresses. Meaning it takes this amount of clock cycles
to complete a loop and completely verify a memory. The test will loop continuously
as long as the test is enabled, providing the added possibility to also use the test for
evaluating the memories’ Single Event Upset (SEU) probability in a irradiation test.
The test is based on writing a fixed pattern, in this case a checkerboard pattern, of
0x2AA to the memory in the first iteration, then in the next iteration it will read and
check the 0x2AA pattern and write back a pattern of 0x155 (the inverse pattern) and
in the next it will check the 0x155 and write 0x2AA and so on [16]. The test algorithm
is similar to the Modified Algorithm Test Sequence (MATS) march algorithm [17].
The algorithms are normally only designed for single port memories, but for testing
of the dual port memories, it can be simplified, as they are in the current design
always written on one side and read on the other. Thus, it is possible to do the read
and write in the same cycle, though not at the same address, so the write is always
lagging one address behind the read.
When an address in the memory is read out and it contains an incorrect value,
the test structure will set a signal high for one clock cycle indicating an error. The
signals indicating an error from each of the test structures are ORed together to
provide a combined output signal. Externally to the device, there are two status
outputs available, a latched single-ended output, and a pulsed differential output.
The pulsed output will give one pulse per address where an error is found on, while
the latched output will stay high until an error is found and will then stay low, enabling
a slower test system to detect an error without the need to sample the pulsed output at
a high speed. The latched output is primarily intended for production testing, while
the pulsed output can for instance be used for SEU detection during radiation testing.
The minimum running time for one test iteration is determined by the largest
memory that runs on the slowest clock, which is the pedestal memory. The decision
on which test to implement is a trade-off between test time and fault coverage. The
5N chequerboard sequence that is implemented does not provide a full coverage of
all possible errors, but is fast, requiring only 256 µs when operated with input clocks
of 320 MHz and 20 MHz for the serial clock and ADC clock respectively.
The chequerboard tester implemented is primarily able to detect:
Stuck-at faults A stuck-at fault occurs when the value of a cell or line is always
0 (a stuck-at-0 fault) or always 1 (a stuck-at-1 fault).
Stuck-open faults The connection to a cell is broken returning the previous read
value.
Address decoding faults Faults present in the address decoding logic. This
includes failure to access a cell located at an address, shorts between addresses,
stuck-at address lines, and stuck-open address lines.
However, it is not able to, or only partly able to detect:
Coupling faults A write to one cell changes the content of a second cell. This
includes a transition in one cell that inverts another cell, a transition in one cell
that forces a 0 or 1 in the other cell, and state coupling faults where a cell is only
79
The algorithm used for testing is a 5N length test (3N for dual port memory),
where N is the number of addresses. Meaning it takes this amount of clock cycles
to complete a loop and completely verify a memory. The test will loop continuously
as long as the test is enabled, providing the added possibility to also use the test for
evaluating the memories’ Single Event Upset (SEU) probability in a irradiation test.
The test is based on writing a fixed pattern, in this case a checkerboard pattern, of
0x2AA to the memory in the first iteration, then in the next iteration it will read and
check the 0x2AA pattern and write back a pattern of 0x155 (the inverse pattern) and
in the next it will check the 0x155 and write 0x2AA and so on [16]. The test algorithm
is similar to the Modified Algorithm Test Sequence (MATS) march algorithm [17].
The algorithms are normally only designed for single port memories, but for testing
of the dual port memories, it can be simplified, as they are in the current design
always written on one side and read on the other. Thus, it is possible to do the read
and write in the same cycle, though not at the same address, so the write is always
lagging one address behind the read.
When an address in the memory is read out and it contains an incorrect value,
the test structure will set a signal high for one clock cycle indicating an error. The
signals indicating an error from each of the test structures are ORed together to
provide a combined output signal. Externally to the device, there are two status
outputs available, a latched single-ended output, and a pulsed differential output.
The pulsed output will give one pulse per address where an error is found on, while
the latched output will stay high until an error is found and will then stay low, enabling
a slower test system to detect an error without the need to sample the pulsed output at
a high speed. The latched output is primarily intended for production testing, while
the pulsed output can for instance be used for SEU detection during radiation testing.
The minimum running time for one test iteration is determined by the largest
memory that runs on the slowest clock, which is the pedestal memory. The decision
on which test to implement is a trade-off between test time and fault coverage. The
5N chequerboard sequence that is implemented does not provide a full coverage of
all possible errors, but is fast, requiring only 256 µs when operated with input clocks
of 320 MHz and 20 MHz for the serial clock and ADC clock respectively.
The chequerboard tester implemented is primarily able to detect:
Stuck-at faults A stuck-at fault occurs when the value of a cell or line is always
0 (a stuck-at-0 fault) or always 1 (a stuck-at-1 fault).
Stuck-open faults The connection to a cell is broken returning the previous read
value.
Address decoding faults Faults present in the address decoding logic. This
includes failure to access a cell located at an address, shorts between addresses,
stuck-at address lines, and stuck-open address lines.
However, it is not able to, or only partly able to detect:
Coupling faults A write to one cell changes the content of a second cell. This
includes a transition in one cell that inverts another cell, a transition in one cell
that forces a 0 or 1 in the other cell, and state coupling faults where a cell is only