78
3 SAMPA Chip Implementation
are instead exercised through the control of the external clock and reset pins during
the scan test. The memory is exercised in its own test as discussed in the next section.
In a worst-case situation where, after manufacturing, all of, or a large portion of,
the devices are non-operational, it is possible to utilize the scan chain capability for
debugging the issue. The scan chain can be used for dumping the state of the device
as well as injecting values to alter the state. As this was not the case for the SAMPA,
this functionality was not utilized.
3.3.1.1 Scan Observability
The fault coverage of the design could potentially have been higher if more adaptions
to the design would have been done earlier in the design process to help increase
the observability of unreachable parts. Sections of the design, like the JTAG, BIST,
memory, and clock generator have been excluded as they interfered with the controllability of the chain. Additionally, there are pins that go to and from the analogue
section which are not controllable. Assuming that the tool that generates the coverage vectors is able to reach 100 % coverage of the logic that it can observe, the total
coverage would still only be 98.9 % in the version 3 design due to inactive logic and
uncontrollability. To increase the observability for logic that surrounds black-boxed
sections, it is possible to add what is referred to as shadow registers, which observe
each input to the black box. These registers have no operational function when the
design is operating normally, but when the design operates in scan chain mode they
can observe the inputs to the black boxes. In the same way, it is possible to connect
the output of a black-boxed module to a multiplexer together with an output from
a shadow register. The path of the shadow register through the multiplexer is only
enabled in the test mode and so, in this way, the output side is controllable as well.
The same method can be applied to capture data going out and in from pins that
are not accessible outside the device, like for instance the signals to and from the
analogue section.
3.3.2 Memory Built-In Self-Test
The memories used in the SAMPA are dual and single port 8-transistor Static Random
Access Memory (SRAM) IPs provided by ARM [15]. Memory IPs are used for their
higher memory densities, lower power, ease of design and for their proven design.
The IPs that are used do not provide BIST for testing of manufacturing defects, so a
custom built-in memory test has been designed to provide quick pass/fail testing.
The test structure is built as a wrapper surrounding each IP, where the data,
address, and control lines for the memories are multiplexed between the normal data
path and the test structure. The test is initiated by pulling a pin high externally to the
chip.
3 SAMPA Chip Implementation
are instead exercised through the control of the external clock and reset pins during
the scan test. The memory is exercised in its own test as discussed in the next section.
In a worst-case situation where, after manufacturing, all of, or a large portion of,
the devices are non-operational, it is possible to utilize the scan chain capability for
debugging the issue. The scan chain can be used for dumping the state of the device
as well as injecting values to alter the state. As this was not the case for the SAMPA,
this functionality was not utilized.
3.3.1.1 Scan Observability
The fault coverage of the design could potentially have been higher if more adaptions
to the design would have been done earlier in the design process to help increase
the observability of unreachable parts. Sections of the design, like the JTAG, BIST,
memory, and clock generator have been excluded as they interfered with the controllability of the chain. Additionally, there are pins that go to and from the analogue
section which are not controllable. Assuming that the tool that generates the coverage vectors is able to reach 100 % coverage of the logic that it can observe, the total
coverage would still only be 98.9 % in the version 3 design due to inactive logic and
uncontrollability. To increase the observability for logic that surrounds black-boxed
sections, it is possible to add what is referred to as shadow registers, which observe
each input to the black box. These registers have no operational function when the
design is operating normally, but when the design operates in scan chain mode they
can observe the inputs to the black boxes. In the same way, it is possible to connect
the output of a black-boxed module to a multiplexer together with an output from
a shadow register. The path of the shadow register through the multiplexer is only
enabled in the test mode and so, in this way, the output side is controllable as well.
The same method can be applied to capture data going out and in from pins that
are not accessible outside the device, like for instance the signals to and from the
analogue section.
3.3.2 Memory Built-In Self-Test
The memories used in the SAMPA are dual and single port 8-transistor Static Random
Access Memory (SRAM) IPs provided by ARM [15]. Memory IPs are used for their
higher memory densities, lower power, ease of design and for their proven design.
The IPs that are used do not provide BIST for testing of manufacturing defects, so a
custom built-in memory test has been designed to provide quick pass/fail testing.
The test structure is built as a wrapper surrounding each IP, where the data,
address, and control lines for the memories are multiplexed between the normal data
path and the test structure. The test is initiated by pulling a pin high externally to the
chip.