76
3 SAMPA Chip Implementation
specifications. Therefore, there is a need to verify the functionality, preferably after
completing each step, so that you end up with a fully functional system. Catching
the bad devices earlier in the process can save on costs, as fewer devices would need
to be processed in the following steps.
Due to the large number of devices that will be needed for the final production
of the SAMPA, and due to the increase in complexity of the device compared to
its predecessors, it is not feasible to test the device fully in a reasonable time frame
only by verifying the functionality through operating the device and changing its
configuration. Since the device also employs various error correcting techniques to
combat SEUs, as further discussed in Sect. 3.4, errors from manufacturing defects
might end up being masked by the error correcting, but will still affect the SEU
tolerance of the device. Due to this, the design has been implemented with several
design-for-test features.
7
To detect errors in manufacturing of the ASIC, the design is implemented with
scan chain capability. When a certain configuration is enabled, all registers in the
design are stringed together into five chains. By manipulating input signals, shifting
bits through the chain, and analysing the output signals, it is possible to exercise most
of the logic in the design and thereby verifying that there are no broken connections
or elements.
The memories in the device are made by a third party and do not support any
scan-chain capability. Instead, a dedicated test structure has been created to verify
their functionality.
To verify that the input/output pads of the ASIC has been properly bonded to the
pins of the package, and to verify there is a proper connection between the package
pins and the printed circuit board once the device is soldered-on, a Joint Test Action
Group (JTAG) boundary scan functionality has been implemented. Through a simple
standardized interface, it is then possible to exercise digital output pins of the device
and read digital input pins.
The analogue section and ADC are not implemented with any built-in test functionality; it therefore requires a functioning digital section for verification. The testing
is primarily limited to observing that the baseline of the channel is within expected
limits, that the channel responds to input signals and that the pulse gain is as expected
from the setting and provided input signal.
3.3.1 Scan Chain
In a scan-enabled design, the registers (flip-flops) are connected together in one or
more scan chains. This enables enable access to the internal nodes of the design from
outside. By shifting patterns into the input of the chain, the state of the design is set
up in a particular way. By advancing the state of the system by one clock cycle, the
7 When features are added to a design with the primary purpose of verifying the functionality of the
device, it is commonly referred to as design-for-test.
3 SAMPA Chip Implementation
specifications. Therefore, there is a need to verify the functionality, preferably after
completing each step, so that you end up with a fully functional system. Catching
the bad devices earlier in the process can save on costs, as fewer devices would need
to be processed in the following steps.
Due to the large number of devices that will be needed for the final production
of the SAMPA, and due to the increase in complexity of the device compared to
its predecessors, it is not feasible to test the device fully in a reasonable time frame
only by verifying the functionality through operating the device and changing its
configuration. Since the device also employs various error correcting techniques to
combat SEUs, as further discussed in Sect. 3.4, errors from manufacturing defects
might end up being masked by the error correcting, but will still affect the SEU
tolerance of the device. Due to this, the design has been implemented with several
design-for-test features.
7
To detect errors in manufacturing of the ASIC, the design is implemented with
scan chain capability. When a certain configuration is enabled, all registers in the
design are stringed together into five chains. By manipulating input signals, shifting
bits through the chain, and analysing the output signals, it is possible to exercise most
of the logic in the design and thereby verifying that there are no broken connections
or elements.
The memories in the device are made by a third party and do not support any
scan-chain capability. Instead, a dedicated test structure has been created to verify
their functionality.
To verify that the input/output pads of the ASIC has been properly bonded to the
pins of the package, and to verify there is a proper connection between the package
pins and the printed circuit board once the device is soldered-on, a Joint Test Action
Group (JTAG) boundary scan functionality has been implemented. Through a simple
standardized interface, it is then possible to exercise digital output pins of the device
and read digital input pins.
The analogue section and ADC are not implemented with any built-in test functionality; it therefore requires a functioning digital section for verification. The testing
is primarily limited to observing that the baseline of the channel is within expected
limits, that the channel responds to input signals and that the pulse gain is as expected
from the setting and provided input signal.
3.3.1 Scan Chain
In a scan-enabled design, the registers (flip-flops) are connected together in one or
more scan chains. This enables enable access to the internal nodes of the design from
outside. By shifting patterns into the input of the chain, the state of the design is set
up in a particular way. By advancing the state of the system by one clock cycle, the
7 When features are added to a design with the primary purpose of verifying the functionality of the
device, it is commonly referred to as design-for-test.