3.2 Digital Implementation
75
The control circuitry for the serialization is protected from Single Event Upsets
(SEUs), as further discussed in Sect. 3.4.1, but the internal generation of the ADC
sampling clock is not. This can be problematic for detectors that need to have the
sampling clock in phase across several devices. To mitigate this, the spare 11th serial
link is used to transmit the ADC clock together with the data stream. An SEU in
one of the ADC clock derivation registers will present itself as a phase shift in the
clock. By counting the number of high and low cycles on the receiving end of the
11th link, it is possible to determine if an SEU has occurred and from there it can be
considered if the device will need to be reset.
This serialization method has the benefit that it is simple to implement a receiver
for it on the upstream device. It also opens the possibility for implementing other
compression forms and filtering methods that are more suited to the detector application, with a trade-off in added development time. The filtering and compression
can be done separately on the front-end card by use of an FPGA. However, it has
the drawback of increased power consumption of the front-end card and the added
effort of radiation qualification of the FPGA device. It can also be done off-board by
sending the data through the GBTx to a readout device. The drawback then will be
that there will be an increase in cost in the form of a need for extra GBTx devices and
optical fibre links. Since there is no error correction added in the data itself and there
is no synchronization during the data transmission, it is up to the upstream device to
verify the integrity of the link during the initial 32-cycle sync pattern. As all serial
links will toggle in a predetermined pattern, it can be verified that none of the links
are stuck at a fixed value.
3.2.6.4 Direct Readout—Combinatorial
For applications where there is only a need to use a subset of the channels the
device provides, a mode is available where the data from the ADC channel inputs
are multiplexed to the 10 serial link outputs. The channel that should be used is
determined through the configuration of five inputs pins. Data from several channels
can be acquired by cycling through input pin configurations during a sampling cycle.
As the configuration pins for setting the channel are single-ended CMOS, the cycling
speed would be limited to the single-ended switching speed of the driving device.
Since the data rate using this method is much lower than with the other methods, it
opens up the possibility to interface the device to low cost FPGA or a microcontroller
solutions.
3.3 Design for Test
The production, manufacturing, and packaging of ASICs, as well as the soldering
of packaged devices on to printed circuit boards, are all imperfect processes where
there is a probability of ending up with a device that does not operate according to
75
The control circuitry for the serialization is protected from Single Event Upsets
(SEUs), as further discussed in Sect. 3.4.1, but the internal generation of the ADC
sampling clock is not. This can be problematic for detectors that need to have the
sampling clock in phase across several devices. To mitigate this, the spare 11th serial
link is used to transmit the ADC clock together with the data stream. An SEU in
one of the ADC clock derivation registers will present itself as a phase shift in the
clock. By counting the number of high and low cycles on the receiving end of the
11th link, it is possible to determine if an SEU has occurred and from there it can be
considered if the device will need to be reset.
This serialization method has the benefit that it is simple to implement a receiver
for it on the upstream device. It also opens the possibility for implementing other
compression forms and filtering methods that are more suited to the detector application, with a trade-off in added development time. The filtering and compression
can be done separately on the front-end card by use of an FPGA. However, it has
the drawback of increased power consumption of the front-end card and the added
effort of radiation qualification of the FPGA device. It can also be done off-board by
sending the data through the GBTx to a readout device. The drawback then will be
that there will be an increase in cost in the form of a need for extra GBTx devices and
optical fibre links. Since there is no error correction added in the data itself and there
is no synchronization during the data transmission, it is up to the upstream device to
verify the integrity of the link during the initial 32-cycle sync pattern. As all serial
links will toggle in a predetermined pattern, it can be verified that none of the links
are stuck at a fixed value.
3.2.6.4 Direct Readout—Combinatorial
For applications where there is only a need to use a subset of the channels the
device provides, a mode is available where the data from the ADC channel inputs
are multiplexed to the 10 serial link outputs. The channel that should be used is
determined through the configuration of five inputs pins. Data from several channels
can be acquired by cycling through input pin configurations during a sampling cycle.
As the configuration pins for setting the channel are single-ended CMOS, the cycling
speed would be limited to the single-ended switching speed of the driving device.
Since the data rate using this method is much lower than with the other methods, it
opens up the possibility to interface the device to low cost FPGA or a microcontroller
solutions.
3.3 Design for Test
The production, manufacturing, and packaging of ASICs, as well as the soldering
of packaged devices on to printed circuit boards, are all imperfect processes where
there is a probability of ending up with a device that does not operate according to