74
3 SAMPA Chip Implementation
The busy signal is not provided with a delay chain as the signal is level based. A
delay in the reception of the busy signal of one or two cycles due to metastability in
the synchronizer is not considered a problem.
To recover from communication errors during transmission between the devices,
the receiving unit does Hamming correction on the received headers. Errors are
corrected before storing in ring buffer for retransmission. In case of the detection of
double errors, the receiving unit drops the data and waits for resynchronization. The
receiving unit can also detect a stuck high/low data input.
When the daisy chaining option is not in use, the units relating to the daisy chaining
is turned off, through clock gating, to save power.
A drawback of this readout method is that if there is a malfunction of one of the
devices in a chain that makes it inoperable, there will also be no data received from
the previous devices in the chain. It is also vulnerable to channels or devices that are
overproducing data, either through misconfiguration or from malfunctioning input
channels. Options are available to turn off misbehaving channels, but monitoring
must be in place upstream to detect and reconfigure the device. In case a device is
partly operational, it is possible to configure it so that the complete device is bypassed
by forwarding the control and data signal directly from input to output.
3.2.6.3 Direct Readout—Serialization
For detectors that would prefer not to use the data handling capabilities of the
SAMPA, a mode is available where the raw ADC samples are directly serialized
and the rest of the digital circuitry is powered down through clock gating. This mode
operates with a serialization speed of 32 times the ADC sampling speed and can be
configured in two modes, referred to as the normal mode and the split mode.
In the normal mode, the 10-bit data for channel 0 will be output in parallel on the
serial links. In the consecutive cycle, the data for channel 1 will be put out, and so
on. Since the serialization speed is 32 times the ADC sampling speed, it is possible
to transmit the current sample for all of the 32 channels in the time it takes to sample
the next sample.
In the split mode, five first serial links are dedicated to channel 0-15 and the other
five serial links are dedicated to channel 16-31. The serialization speed is still 32
times the ADC sampling speed, but it takes two serialization cycles to transmit a
full sample. In the first cycle, the 5 lower bits for channel 0 and the 5 lower bits for
channel 16 will be transmitted. On the consecutive cycle, the 5 upper bits for the
same channels are transmitted, it then continues with the 5 lower bits for the next
channel, and so on. In this way, it is possible to direct the data for half the channels
to one upstream receiver and the other half to another.
Upon start up, a 32-cycle sync pattern is transmitted, so that the receiving end
can synchronize to the stream. As the data transmission is cyclic, there is no need
to have a separate data bit to indicate the start of a new sample. If the receiver loses
track, it can restart the transmission to get a new sync word without losing more than
a couple of samples.
3 SAMPA Chip Implementation
The busy signal is not provided with a delay chain as the signal is level based. A
delay in the reception of the busy signal of one or two cycles due to metastability in
the synchronizer is not considered a problem.
To recover from communication errors during transmission between the devices,
the receiving unit does Hamming correction on the received headers. Errors are
corrected before storing in ring buffer for retransmission. In case of the detection of
double errors, the receiving unit drops the data and waits for resynchronization. The
receiving unit can also detect a stuck high/low data input.
When the daisy chaining option is not in use, the units relating to the daisy chaining
is turned off, through clock gating, to save power.
A drawback of this readout method is that if there is a malfunction of one of the
devices in a chain that makes it inoperable, there will also be no data received from
the previous devices in the chain. It is also vulnerable to channels or devices that are
overproducing data, either through misconfiguration or from malfunctioning input
channels. Options are available to turn off misbehaving channels, but monitoring
must be in place upstream to detect and reconfigure the device. In case a device is
partly operational, it is possible to configure it so that the complete device is bypassed
by forwarding the control and data signal directly from input to output.
3.2.6.3 Direct Readout—Serialization
For detectors that would prefer not to use the data handling capabilities of the
SAMPA, a mode is available where the raw ADC samples are directly serialized
and the rest of the digital circuitry is powered down through clock gating. This mode
operates with a serialization speed of 32 times the ADC sampling speed and can be
configured in two modes, referred to as the normal mode and the split mode.
In the normal mode, the 10-bit data for channel 0 will be output in parallel on the
serial links. In the consecutive cycle, the data for channel 1 will be put out, and so
on. Since the serialization speed is 32 times the ADC sampling speed, it is possible
to transmit the current sample for all of the 32 channels in the time it takes to sample
the next sample.
In the split mode, five first serial links are dedicated to channel 0-15 and the other
five serial links are dedicated to channel 16-31. The serialization speed is still 32
times the ADC sampling speed, but it takes two serialization cycles to transmit a
full sample. In the first cycle, the 5 lower bits for channel 0 and the 5 lower bits for
channel 16 will be transmitted. On the consecutive cycle, the 5 upper bits for the
same channels are transmitted, it then continues with the 5 lower bits for the next
channel, and so on. In this way, it is possible to direct the data for half the channels
to one upstream receiver and the other half to another.
Upon start up, a 32-cycle sync pattern is transmitted, so that the receiving end
can synchronize to the stream. As the data transmission is cyclic, there is no need
to have a separate data bit to indicate the start of a new sample. If the receiver loses
track, it can restart the transmission to get a new sync word without losing more than
a couple of samples.