3.2 Digital Implementation
73
SAMPA 1
SAMPA 2
SAMPA 3
NBflowstop_in
SerialOut[0]
NBflowstop_in
SerialOut[0]
DinN
NBflowstop_out_SO5
SerialOut[0]
DinN
NBflowstop_out_SO5
Fig. 3.20 Connection setup for daisy chaining
When the busy signal is high, it tells the upstream device to halt its transmission of
data after the current packet is done. While waiting to send data again the upstream
device will send sync packets to keep the communication in sync.
The downstream device has the serial output of the upstream device connected to
its daisy input port. Sync packets arriving on the link are filtered out and only heartbeat
packets and data packets are forwarded. The accepted packets from the upstream
device are added to a ring buffer in the same way as for the internal channels. A
configuration register defines how many upstream devices there are from the current
device. This value is used by the serialization module that serializes packets from the
ring buffers for defining the number of packets that should be forwarded from the
upstream link before a packet from one of the internal channels can be forwarded.
The handshaking between the serial link module and the module that handles the
readout of the buffers is however constructed in a way that it is not possible to read
out two consecutive packets from the same buffer without a few cycles delay, which
causes there to be sent a sync packet in between two packets from the upstream
device when this setting is enabled. In principle there is no limiting factor to fix it
in the existing buffer readout module, but there would need to be an addition of an
extra state machine in the buffer readout module that pre-reads the next header from
memory so that it is ready to be transmitted. The primary issue however lies in that
the data ready signal from the buffer also is used to indicate that a stream of data
is completed and that the serializer should select another buffer or a sync packet to
send, but this could be solved by separating the data ready and packet done signal.
Since the MCH will only operate with two devices in a chain, this was not prioritized
to be fixed for the SAMPA v3.
Commonly, all the devices in a chain will be clocked from the same source. As
the data is sent and captured at the same clock speed, it is possible that the data
stream could be corrupted after exiting the synchronizer on the receiving end if the
data that is received changes too close to the clock edge causing metastability in
the synchronizer. Since the time between data being clocked out of the upstream
device to it is received on the downstream device is dependent on various factors
such as the distance between the devices, the properties of the Printed Circuit Board
(PCB) material, the process variation of the device etc. a programmable delay chain
has been added before the signal enters the synchronizer. The incoming data can be
delayed by up to 12.5 ns in steps of 0.2 ns. The maximum length allows for delaying
the signal by a full clock cycle at 80 MHz and provides enough of a granularity to
allow for 15 steps of delay at 320 MHz.
73
SAMPA 1
SAMPA 2
SAMPA 3
NBflowstop_in
SerialOut[0]
NBflowstop_in
SerialOut[0]
DinN
NBflowstop_out_SO5
SerialOut[0]
DinN
NBflowstop_out_SO5
Fig. 3.20 Connection setup for daisy chaining
When the busy signal is high, it tells the upstream device to halt its transmission of
data after the current packet is done. While waiting to send data again the upstream
device will send sync packets to keep the communication in sync.
The downstream device has the serial output of the upstream device connected to
its daisy input port. Sync packets arriving on the link are filtered out and only heartbeat
packets and data packets are forwarded. The accepted packets from the upstream
device are added to a ring buffer in the same way as for the internal channels. A
configuration register defines how many upstream devices there are from the current
device. This value is used by the serialization module that serializes packets from the
ring buffers for defining the number of packets that should be forwarded from the
upstream link before a packet from one of the internal channels can be forwarded.
The handshaking between the serial link module and the module that handles the
readout of the buffers is however constructed in a way that it is not possible to read
out two consecutive packets from the same buffer without a few cycles delay, which
causes there to be sent a sync packet in between two packets from the upstream
device when this setting is enabled. In principle there is no limiting factor to fix it
in the existing buffer readout module, but there would need to be an addition of an
extra state machine in the buffer readout module that pre-reads the next header from
memory so that it is ready to be transmitted. The primary issue however lies in that
the data ready signal from the buffer also is used to indicate that a stream of data
is completed and that the serializer should select another buffer or a sync packet to
send, but this could be solved by separating the data ready and packet done signal.
Since the MCH will only operate with two devices in a chain, this was not prioritized
to be fixed for the SAMPA v3.
Commonly, all the devices in a chain will be clocked from the same source. As
the data is sent and captured at the same clock speed, it is possible that the data
stream could be corrupted after exiting the synchronizer on the receiving end if the
data that is received changes too close to the clock edge causing metastability in
the synchronizer. Since the time between data being clocked out of the upstream
device to it is received on the downstream device is dependent on various factors
such as the distance between the devices, the properties of the Printed Circuit Board
(PCB) material, the process variation of the device etc. a programmable delay chain
has been added before the signal enters the synchronizer. The incoming data can be
delayed by up to 12.5 ns in steps of 0.2 ns. The maximum length allows for delaying
the signal by a full clock cycle at 80 MHz and provides enough of a granularity to
allow for 15 steps of delay at 320 MHz.