54
3 SAMPA Chip Implementation
parameters of each channel for the optimal filtering. In the previous devices, only a
limited set of parameters were available for configuration on a per channel basis.
Access to the channel registers is done through the global register via a data input,
data output, address, and operational control register. The information in the control
register indicates which channel to access and if the operation is a read or write action.
The order of the registers in the global register has been designed to minimize the
amount of writes needed to update a channel register. As seen in Table 3.2, the address
in the channel register address
5 to access is followed by the write data. which is again
followed by the access control register. By utilizing the multi-byte write feature of
the I
2 C, a channel register can be updated in one continuous I
2 C transaction. To write
the same information to all channels, a broadcast bit can be enabled to broadcast the
write action to all channels.
The device contains a 1024-word memory per channel, called the pedestal memory, which is primarily used for data corrections, further discussed in Sect. 3.2.3.1.
The read and write port for the memories are accessible through the channel register,
but the address port for the memory is shared among all channels and is accessible from the global register. To minimize the amount of writes needed to update
the memories an auto-increment feature has been added for the pedestal memory
address so that on each write to the access control register the pedestal memory
address can be automatically increased without needing to update two more registers. Combined with the broadcasting of a channel register write to all channels, a
full pedestal memory can be updated in 5 k 8-bit transactions corresponding to about
48 ms at 1 MHz.
For rerouting of input channels to specific serial links, the device contains a
programmable register for defining the ordering, called the channel order register,
further discussed in Sect. 3.2.6.1. The register is directly accessible through the global
register via lookup. To save one address, only one address is used for the data during
both read and write access. Like for the channel registers, the registers used for
accessing the channel order registers are arranged to support a quick update.
Further information on the registers can be found in Appendix B.
3.2.3 Digital Signal Conditioning
To increase the efficiency of the lossy data compression algorithms and to facilitate
easier analysis of the data during the final event-reconstruction, the sample data
passes through some Digital Signal Conditioning (DSC). The DSC implements, in
a pipelined manner, different algorithms to condition and shape the signal, and is
comprised of four main building blocks
Baseline Correction 1 (BC1) This first filtering stage’s main task is to remove
low frequency perturbations and systematic effects. Different modes of operation
are available, depending on the application.
5 CHRGADD.
3 SAMPA Chip Implementation
parameters of each channel for the optimal filtering. In the previous devices, only a
limited set of parameters were available for configuration on a per channel basis.
Access to the channel registers is done through the global register via a data input,
data output, address, and operational control register. The information in the control
register indicates which channel to access and if the operation is a read or write action.
The order of the registers in the global register has been designed to minimize the
amount of writes needed to update a channel register. As seen in Table 3.2, the address
in the channel register address
5 to access is followed by the write data. which is again
followed by the access control register. By utilizing the multi-byte write feature of
the I
2 C, a channel register can be updated in one continuous I
2 C transaction. To write
the same information to all channels, a broadcast bit can be enabled to broadcast the
write action to all channels.
The device contains a 1024-word memory per channel, called the pedestal memory, which is primarily used for data corrections, further discussed in Sect. 3.2.3.1.
The read and write port for the memories are accessible through the channel register,
but the address port for the memory is shared among all channels and is accessible from the global register. To minimize the amount of writes needed to update
the memories an auto-increment feature has been added for the pedestal memory
address so that on each write to the access control register the pedestal memory
address can be automatically increased without needing to update two more registers. Combined with the broadcasting of a channel register write to all channels, a
full pedestal memory can be updated in 5 k 8-bit transactions corresponding to about
48 ms at 1 MHz.
For rerouting of input channels to specific serial links, the device contains a
programmable register for defining the ordering, called the channel order register,
further discussed in Sect. 3.2.6.1. The register is directly accessible through the global
register via lookup. To save one address, only one address is used for the data during
both read and write access. Like for the channel registers, the registers used for
accessing the channel order registers are arranged to support a quick update.
Further information on the registers can be found in Appendix B.
3.2.3 Digital Signal Conditioning
To increase the efficiency of the lossy data compression algorithms and to facilitate
easier analysis of the data during the final event-reconstruction, the sample data
passes through some Digital Signal Conditioning (DSC). The DSC implements, in
a pipelined manner, different algorithms to condition and shape the signal, and is
comprised of four main building blocks
Baseline Correction 1 (BC1) This first filtering stage’s main task is to remove
low frequency perturbations and systematic effects. Different modes of operation
are available, depending on the application.
5 CHRGADD.