3.2 Digital Implementation
55
Table 3.2 Registers used for accessing the channel registers, channel ordering registers and pedestal
memories. The order of the registers has been arranged to minimize the amount of writes needed
to update a channel register
Register name
Address Type
Default Description
PMADDL
[7:0]
0x15
RW
0x00
[7:0]
Pedestal memory address,
lower byte
PMADDH
[1:0]
0x16
RW
0x00
[1:0]
Pedestal memory address,
upper byte
CHRGADD
[4:0]
0x17
RW
0x00
[4:0]
Channel register address
CHRGWDATL [7:0]
0x18
RW
0x00
[7:0]
Channel register write data,
lower byte
CHRGWDATH [4:0]
0x19
RW
0x00
[4:0]
Channel register write data,
upper byte
CHRGCTL
[7:0]
0x1A
RW
0x00
Channel register control
RW
0x00
[4:0]
Channel number
RW
0x00
[5]
Broadcast to all channels
(channel number ignored)
RW
0x00
[6]
Write, not read from
register address (returns to
read after write)
RW
0x00
[7]
Increment PMADD (returns
automatically to zero)
CHRGRDATL [7:0]
0x1B
R
0x00
[7:0]
Channel register read data,
lower byte
CHRGRDATH [4:0]
0x1C
R
0x00
[4:0]
Channel register read data,
upper byte
CHORDAT
[4:0]
0x1D
RW
0x00
[4:0]
Channel readout order data
CHORDCTL
[5:0]
0x1E
RW
0x00
Channel readout order
control
RW
0x00
[4:0]
Position in order
RW
0x00
[5]
Write enable
Digital Shaper (DS) This filter can be used for three different applications; tail
cancellation, peaking time correction, or as a general purpose low-/high-/bandpass or band-stop filter. It is implemented as fourth-order Infinite Impulse
Response (IIR) filter, specifically tailored for the two first applications, but can
be reconfigured as a general second-order IIR filter for general purpose filtering.
Baseline Correction 2 (BC2) This unit applies a baseline correction based on a
moving average filter. It can remove non-systematic perturbations of the baseline
that are superimposed on to the signal.
Baseline Correction 3 (BC3) This unit applies a baseline correction through a
slope based filter. It is provided as a more stable alternative to the BC2 filter.
55
Table 3.2 Registers used for accessing the channel registers, channel ordering registers and pedestal
memories. The order of the registers has been arranged to minimize the amount of writes needed
to update a channel register
Register name
Address Type
Default Description
PMADDL
[7:0]
0x15
RW
0x00
[7:0]
Pedestal memory address,
lower byte
PMADDH
[1:0]
0x16
RW
0x00
[1:0]
Pedestal memory address,
upper byte
CHRGADD
[4:0]
0x17
RW
0x00
[4:0]
Channel register address
CHRGWDATL [7:0]
0x18
RW
0x00
[7:0]
Channel register write data,
lower byte
CHRGWDATH [4:0]
0x19
RW
0x00
[4:0]
Channel register write data,
upper byte
CHRGCTL
[7:0]
0x1A
RW
0x00
Channel register control
RW
0x00
[4:0]
Channel number
RW
0x00
[5]
Broadcast to all channels
(channel number ignored)
RW
0x00
[6]
Write, not read from
register address (returns to
read after write)
RW
0x00
[7]
Increment PMADD (returns
automatically to zero)
CHRGRDATL [7:0]
0x1B
R
0x00
[7:0]
Channel register read data,
lower byte
CHRGRDATH [4:0]
0x1C
R
0x00
[4:0]
Channel register read data,
upper byte
CHORDAT
[4:0]
0x1D
RW
0x00
[4:0]
Channel readout order data
CHORDCTL
[5:0]
0x1E
RW
0x00
Channel readout order
control
RW
0x00
[4:0]
Position in order
RW
0x00
[5]
Write enable
Digital Shaper (DS) This filter can be used for three different applications; tail
cancellation, peaking time correction, or as a general purpose low-/high-/bandpass or band-stop filter. It is implemented as fourth-order Infinite Impulse
Response (IIR) filter, specifically tailored for the two first applications, but can
be reconfigured as a general second-order IIR filter for general purpose filtering.
Baseline Correction 2 (BC2) This unit applies a baseline correction based on a
moving average filter. It can remove non-systematic perturbations of the baseline
that are superimposed on to the signal.
Baseline Correction 3 (BC3) This unit applies a baseline correction through a
slope based filter. It is provided as a more stable alternative to the BC2 filter.