3.2 Digital Implementation
51
D Q
D Q
D Q
D Q
'1'
async
async
async
async
clk_config[3] mux output
400-800ps
delay
D Q
D Q
Serial clk un-gated
'1'
Reset pin
Power on reset pin
async
async
Hard reset serial clk
400-800ps
delay
Reset primary clock dividers
Reset primary clock divider
Reset ADC clock divider
Reset manager
Fig. 3.7 Schematic diagram of the reset for the clock generation tree
A soft reset signal is provided through a global register accessible via the slow
control. The soft reset will reset everything except the clock generators and the
configuration registers. In this way, the device can be reset to a known state without
having to reconfigure it. The memories in the device are not reset or initialized in
any way and will therefore retain their data even through a hard reset. The flip-flop
circuitry connected to the soft reset line in Fig. 3.6 was added to make sure the I
2 C
acknowledge of the soft reset command is transmitted before a reset takes place.
When relying on the power-on-reset to get the device into a known state, the
devices across a detector will likely not start up at exactly the same time as this
depends on when the devices receive power, which can be difficult to synchronize
if there are several power supplies that might have different loads. When deriving
the sampling clock from a higher speed clock internally to the device, the phase of
the sampling clock will be dependent on when the device was reset. If the devices
have not started up at the same time, there will likely be a phase difference in the
sampling clock between devices as well, which normally is undesirable. Since the
reset manager has been made with a predictable constant start-up delay, the devices
across a detector can be reset, and the sampling clocks brought in phase, by applying
the reset to all devices at the same time. The primary clock and the hard reset can be
propagated to the device with minimal skew between devices, at least when using the
GBTx, as long as the length of the optical fibres connected to the GBTx are of equal
length. With their propagation delay of about 5 ns/m, they are the largest contributor
to the skew. Trace lengths on the front-end boards also has a minor impact, but this
can normally be compensated for when designing the boards. As the reset happens
synchronously to the clock, there is the option to compensate for the skew by applying
the reset signal one or more cycle earlier or later to certain boards, which gives a
skew compensation granularity of 3.125 ns at the highest data rate. If the skew in the
optical fibre length is not known to a high degree, the device provides the option
3 to
3 This option is provided by the Bypass register, see Sect. B.1.9.
51
D Q
D Q
D Q
D Q
'1'
async
async
async
async
clk_config[3] mux output
400-800ps
delay
D Q
D Q
Serial clk un-gated
'1'
Reset pin
Power on reset pin
async
async
Hard reset serial clk
400-800ps
delay
Reset primary clock dividers
Reset primary clock divider
Reset ADC clock divider
Reset manager
Fig. 3.7 Schematic diagram of the reset for the clock generation tree
A soft reset signal is provided through a global register accessible via the slow
control. The soft reset will reset everything except the clock generators and the
configuration registers. In this way, the device can be reset to a known state without
having to reconfigure it. The memories in the device are not reset or initialized in
any way and will therefore retain their data even through a hard reset. The flip-flop
circuitry connected to the soft reset line in Fig. 3.6 was added to make sure the I
2 C
acknowledge of the soft reset command is transmitted before a reset takes place.
When relying on the power-on-reset to get the device into a known state, the
devices across a detector will likely not start up at exactly the same time as this
depends on when the devices receive power, which can be difficult to synchronize
if there are several power supplies that might have different loads. When deriving
the sampling clock from a higher speed clock internally to the device, the phase of
the sampling clock will be dependent on when the device was reset. If the devices
have not started up at the same time, there will likely be a phase difference in the
sampling clock between devices as well, which normally is undesirable. Since the
reset manager has been made with a predictable constant start-up delay, the devices
across a detector can be reset, and the sampling clocks brought in phase, by applying
the reset to all devices at the same time. The primary clock and the hard reset can be
propagated to the device with minimal skew between devices, at least when using the
GBTx, as long as the length of the optical fibres connected to the GBTx are of equal
length. With their propagation delay of about 5 ns/m, they are the largest contributor
to the skew. Trace lengths on the front-end boards also has a minor impact, but this
can normally be compensated for when designing the boards. As the reset happens
synchronously to the clock, there is the option to compensate for the skew by applying
the reset signal one or more cycle earlier or later to certain boards, which gives a
skew compensation granularity of 3.125 ns at the highest data rate. If the skew in the
optical fibre length is not known to a high degree, the device provides the option
3 to
3 This option is provided by the Bypass register, see Sect. B.1.9.