The operation of several fabricated chip versions requires a significant hardware
and software infrastructure to physically send slow control data and timing (clock,
synchronization) to the chip and to receive the multiple fast data streams sent by the
chip. Dr. Velure achieved this by connecting the chip to a programmable logic
circuit (field programmable gate array, FPGA), by creating suited firmware to
operate the FPGA and by developing software to control the FPGA and to analyse
and visualize the acquired data. This effort was vital in characterizing the device
and ensuring that the manufactured devices were produced without fault, so that
sub-par devices would not be installed in the experiment, affecting the quality of
physics results for many years to come.
The thesis work was performed at the Department of Physics and Technology,
University of Bergen, between 05/2013 and 10/2017, leading to several publications and presentations in international conferences, and was honoured as best PhD
thesis by the CERN ALICE collaboration.
Bergen, Norway
January 2021
Prof. Kjetil Ullaland
Prof. Dieter Röhrich
vi
Supervisors’ Foreword
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