Supervisors’ Foreword
This thesis describes a microcircuit, the SAMPA chip, which is presently being
used by ALICE (A Large Ion Collider Experiment), which is an experiment dedicated to heavy-ion physics at the Large Hadron Collider (LHC) at CERN. It is
designed to study the physics of strongly interacting matter at extreme energy
densities, where a phase of matter called quark-gluon plasma forms. In experimental high-energy physics, specialized, custom design circuits are widely used.
The detectors are large and often need a high number of channels to be readout, for
example, the Time Projection Chamber (TPC) has more than 500,000 charge
sensitive pads. Each of these needs a low noise amplifier, pulse shaping filter and
analogue-to-digital converter, as well as digital signal processing, all of which
would require large circuit boards if implemented with standard components. Even
if the functional requirements could be met with such a solution, the physical size,
cooling needs due to high power consumption and other practical and performance
problems would make them highly unattractive.
At the time of writing, the ALICE experiment is being upgraded to take a much
higher Pb-Pb collision rate than previously, and consequently all readout electronics
have to be replaced by solutions with significantly enhanced performance.
Previously data was readout in frames of about 1000 samples triggered by individual particle collisions. But in the upgraded detector, the collision rate is so high
that continuous readout is needed, which results in a much higher data output rate
from the front-end chips (SAMPAs) to the back-end electronics. The SAMPA
front-end chip is one of the most crucial elements in this upgrade and is therefore
essential for ALICE to carry out their foreseen future physics program.
Each SAMPA chip has 32 channels. Every channel contains, among others, a
charge sensitive amplifier-shaper combination, a 10-bit analogue-to-digital converter running at 10 MHz and a digital signal processing chain with various options
for signal baseline stabilization, hit filtering and hit finding. Global infrastructures
are, for instance, an I
2 C slow control system to write and read a multitude of
configuration parameters, a clock distribution and reset network, and a data packer
and serializer which can serve several links of 320 Mbit/s and even daisy chain
chips in case of lower hit rates.
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