Abstract
The A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider at
CERN is upgrading two of its sub-detectors, the Time Projection Chamber and
Muon Chambers, with new front-end electronics to handle the expected higher
Pb-Pb collision-rates in the next running period (Run 3) foreseen to start in 2021.
The higher collision rate requires the detectors to employ a continuous readout
of the data from the front-end, in contrast to the previous triggered readout. The
devices currently employed for the readout of the detectors can only operate in
triggered mode and need to be replaced. A new 32-channel integrated circuit called
SAMPA has been designed to match the requirements of both detectors.
The SAMPA device contains a charge sensitive amplifier, a pulse shaper and a
10-bit 10 MHz analogue-to-digital converter for each channel and a common digital
signal processor part. The digital signal processor provides various signal filtering
and conditioning operations to improve on the data compression ability.
Acquisition can be done in either triggered or continuous mode and the data is
offloaded through 320 Mbps differential serial links, allowing a data throughput of
up to 3.2 Gbps.
The first prototype of the SAMPA was delivered in 2014, the second in 2016 and
the third was delivered in the end of 2017. The final production run was done in
mid-2018 and completed the testing at the end of 2018. FEC production and testing
is underway and the MCH and TPC are ready for installation in mid-2019.
The main purpose of this thesis has been to specify, design, test and verify the
digital signal processing part of the SAMPA device to encompass the needs of the
detectors involved. Innovative solutions have been employed to reduce the bandwidth required by the detectors, as well as adaptations to ease data handling later in
the processing chain.
By means of simulations, test procedures, verification methods and applied
methods for design of reliable systems, a major part of the work has been on
qualifying the design for submission to production. Since the design submission
process and the following production time of the device is quite long and as the
only means of verifying and reading out data from the analogue front-end and the
analogue-to-digital converter is through the digital part of the device, it is of the
vii
The A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider at
CERN is upgrading two of its sub-detectors, the Time Projection Chamber and
Muon Chambers, with new front-end electronics to handle the expected higher
Pb-Pb collision-rates in the next running period (Run 3) foreseen to start in 2021.
The higher collision rate requires the detectors to employ a continuous readout
of the data from the front-end, in contrast to the previous triggered readout. The
devices currently employed for the readout of the detectors can only operate in
triggered mode and need to be replaced. A new 32-channel integrated circuit called
SAMPA has been designed to match the requirements of both detectors.
The SAMPA device contains a charge sensitive amplifier, a pulse shaper and a
10-bit 10 MHz analogue-to-digital converter for each channel and a common digital
signal processor part. The digital signal processor provides various signal filtering
and conditioning operations to improve on the data compression ability.
Acquisition can be done in either triggered or continuous mode and the data is
offloaded through 320 Mbps differential serial links, allowing a data throughput of
up to 3.2 Gbps.
The first prototype of the SAMPA was delivered in 2014, the second in 2016 and
the third was delivered in the end of 2017. The final production run was done in
mid-2018 and completed the testing at the end of 2018. FEC production and testing
is underway and the MCH and TPC are ready for installation in mid-2019.
The main purpose of this thesis has been to specify, design, test and verify the
digital signal processing part of the SAMPA device to encompass the needs of the
detectors involved. Innovative solutions have been employed to reduce the bandwidth required by the detectors, as well as adaptations to ease data handling later in
the processing chain.
By means of simulations, test procedures, verification methods and applied
methods for design of reliable systems, a major part of the work has been on
qualifying the design for submission to production. Since the design submission
process and the following production time of the device is quite long and as the
only means of verifying and reading out data from the analogue front-end and the
analogue-to-digital converter is through the digital part of the device, it is of the
vii