48
3 SAMPA Chip Implementation
The main input serializing clock is primarily used only in the final serialization
before the output links, where it serializes two bits at a time. Double-edged clocking
or a Double Data Rate (DDR) cell would have been useful for the serialization and
de-serialization parts of the design so that there would be one less clock domain to be
distributed across the design. However, double-edged clocking, by using a rising and
falling edge flip-flop together with a multiplexer, adds some additional issues when
designing the scan chain capability,
1 as the scan-chain only operates with singleedged clocking. Those parts of the design would need to be excluded from the chain
or some additional care would have to be taken to change the negative-edged flipflops to positive-edged when the scan-chain functionality is enabled. When doubleedged clocking is in use, there is also the possibility that the duty cycle would be
asymmetrical for the output data, which could lead to capturing issues on the GBTx.
The standard cell libraries for the process did not include DDR cells and a custom
one was not designed due to lack of resources, though in hindsight this functionality
could probably have been included in the custom SLVS driver that was created for
the design.
The clock management is implemented as shown in Fig. 3.5 and is controlled by
seven pins externally to the device. The design has been architectured in such a way
that it is possible to always run with a fixed 40 MHz bunch-crossing clock and keep
a sampling clock speed of either 5, 10 or 20 MHz independent of the input serial
link clock being 80, 160 or 320 MHz. Both the sampling clock and bunch-crossing
clock can be configured to be supplied from an external source. The sampling clock
can additionally be configured to be derived from the bunch-crossing clock input if
it is external or they can both be derived from the serial link clock input. A lookup
table is used to convert the status of three of the control pins into the multiplexer
configuration for the eight valid combinations of serial link speed and sampling speed
as shown in the bottom left of Fig. 3.5.
One of the clock configuration pins is used as a main control for disabling the
clock to a majority of the digital circuitry by clock gating. This is utilized when
operating in the direct readout serialization mode
2 where the functionality of the
design is reduced to the bare minimum to serialize data directly from the ADC. This
saves power and reduces potentially generated noise.
All the required internal frequencies in the device are generated with ripple counters [4], i.e. the frequency is halved in subsequent steps to get the required frequency.
For applications where there is a need for other frequencies, the sampling clock can
be supplied externally instead. Since there were no requirements for specific sampling frequencies that could not be derived from the main clock by factors of two,
a Phase Locked Loop (PLL) is not included due to the extra design complexity that
this would involve.
1 See Sect. 3.3.1 for more information about the scan chain implementation.
2 See Sect. 3.2.6.3 for more information about the direct readout serialization mode.
3 SAMPA Chip Implementation
The main input serializing clock is primarily used only in the final serialization
before the output links, where it serializes two bits at a time. Double-edged clocking
or a Double Data Rate (DDR) cell would have been useful for the serialization and
de-serialization parts of the design so that there would be one less clock domain to be
distributed across the design. However, double-edged clocking, by using a rising and
falling edge flip-flop together with a multiplexer, adds some additional issues when
designing the scan chain capability,
1 as the scan-chain only operates with singleedged clocking. Those parts of the design would need to be excluded from the chain
or some additional care would have to be taken to change the negative-edged flipflops to positive-edged when the scan-chain functionality is enabled. When doubleedged clocking is in use, there is also the possibility that the duty cycle would be
asymmetrical for the output data, which could lead to capturing issues on the GBTx.
The standard cell libraries for the process did not include DDR cells and a custom
one was not designed due to lack of resources, though in hindsight this functionality
could probably have been included in the custom SLVS driver that was created for
the design.
The clock management is implemented as shown in Fig. 3.5 and is controlled by
seven pins externally to the device. The design has been architectured in such a way
that it is possible to always run with a fixed 40 MHz bunch-crossing clock and keep
a sampling clock speed of either 5, 10 or 20 MHz independent of the input serial
link clock being 80, 160 or 320 MHz. Both the sampling clock and bunch-crossing
clock can be configured to be supplied from an external source. The sampling clock
can additionally be configured to be derived from the bunch-crossing clock input if
it is external or they can both be derived from the serial link clock input. A lookup
table is used to convert the status of three of the control pins into the multiplexer
configuration for the eight valid combinations of serial link speed and sampling speed
as shown in the bottom left of Fig. 3.5.
One of the clock configuration pins is used as a main control for disabling the
clock to a majority of the digital circuitry by clock gating. This is utilized when
operating in the direct readout serialization mode
2 where the functionality of the
design is reduced to the bare minimum to serialize data directly from the ADC. This
saves power and reduces potentially generated noise.
All the required internal frequencies in the device are generated with ripple counters [4], i.e. the frequency is halved in subsequent steps to get the required frequency.
For applications where there is a need for other frequencies, the sampling clock can
be supplied externally instead. Since there were no requirements for specific sampling frequencies that could not be derived from the main clock by factors of two,
a Phase Locked Loop (PLL) is not included due to the extra design complexity that
this would involve.
1 See Sect. 3.3.1 for more information about the scan chain implementation.
2 See Sect. 3.2.6.3 for more information about the direct readout serialization mode.