3.2 Digital Implementation
47
The ADCs require sampling clocks of up to 20 MHz and conversion clocks at 16
times the sampling clock speed. The sampling clock is used to start a new conversion
of the analogue input signal into a digital signal, whereas the conversion clock is
used for advancing the state machine that completes the conversion. Internally to
the ADC the conversion clock is doubled, which makes it possible to operate with
a sampling speed of 10 MHz and an input clock of only 80 MHz as required by the
MCH.
For lowering power consumption and potentially generated noise from the digital,
the processing of the sample data in the digital part happens at the selected ADC
sampling speed as well. However, the sampling clocks supplied to the ADCs are
from a different clock root than the one used for the digital. This is done to supply a
cleaner clock to the ADCs in terms of skew and jitter. It also presents the opportunity
to delay the sampling clocks for the ADCs so that the conversion does not occur at
the same time as the digital part is active processing data.
The LHC operates on a synchronized clock, slightly higher than 40 MHZ, called
the bunch-crossing clock. It is named so as the period is equal to the nominal time
between the passings of two bunches of particles in the main accelerator ring. To
synchronize the colliding of two bunches with the produced data in the detector, the
SAMPA keeps an internal counter running at the bunch-crossing clock speed, which
is used to mark when the first sample in a packet occurred. The clocks received from
the GBTx are multiples of the bunch-crossing clock frequency and so an internal
clock is derived from the input clock to operate as the internal bunch-crossing clock.
Since the clock is a fixed frequency for all applications, in contrast to the ADC
sampling clock, the bunch-crossing clock is also used for operation of the I
2 C. This
enables the I
2 C to operate reliably at the highest speed supported by the GBT-SCA
of 1 MHz.
In the section of the digital design that handles readout from the buffer memories
and serialization of the data to the serial links, there is a need for a clock that is
a fixed fraction of the serial clock. This fraction must also be a factor of 10 since
the data is stored in 10-bit words, i.e. the clock needs to be either 1/10, 1/5, 1/2 or
1/1 of the serial clock speed. Since the buffer memories have a maximum operating
speed lower than the maximum serializing speed of 320 MHz, the full speed cannot
be chosen. Instead 1/2 of the serial speed is used due to the ease of generating a 1/2
clock from the input clock by halving, compared to using a 1/10 or a 1/5 clock, which
will require a counter based division, which is more prone to SEE as well. A lower
clock speed has the benefit of generating lower noise and power, but the circuitry
operating on this clock domain is of a small size and physically located furthest away
from the analogue section, so the influence is not significant.
In the section that handles writing to the buffer memory from each processing
channel, a higher clock speed is needed as well because in some cases there is a need
to store some control data at the same time as a sample is received. The same clock
is used in this section as for the output section, since with the output clock as 1/2 the
serializing clock it is always higher than two times the sample clock. This avoids a
separate clock domain, as would be the case if 1/10 or 1/5 would be selected.
47
The ADCs require sampling clocks of up to 20 MHz and conversion clocks at 16
times the sampling clock speed. The sampling clock is used to start a new conversion
of the analogue input signal into a digital signal, whereas the conversion clock is
used for advancing the state machine that completes the conversion. Internally to
the ADC the conversion clock is doubled, which makes it possible to operate with
a sampling speed of 10 MHz and an input clock of only 80 MHz as required by the
MCH.
For lowering power consumption and potentially generated noise from the digital,
the processing of the sample data in the digital part happens at the selected ADC
sampling speed as well. However, the sampling clocks supplied to the ADCs are
from a different clock root than the one used for the digital. This is done to supply a
cleaner clock to the ADCs in terms of skew and jitter. It also presents the opportunity
to delay the sampling clocks for the ADCs so that the conversion does not occur at
the same time as the digital part is active processing data.
The LHC operates on a synchronized clock, slightly higher than 40 MHZ, called
the bunch-crossing clock. It is named so as the period is equal to the nominal time
between the passings of two bunches of particles in the main accelerator ring. To
synchronize the colliding of two bunches with the produced data in the detector, the
SAMPA keeps an internal counter running at the bunch-crossing clock speed, which
is used to mark when the first sample in a packet occurred. The clocks received from
the GBTx are multiples of the bunch-crossing clock frequency and so an internal
clock is derived from the input clock to operate as the internal bunch-crossing clock.
Since the clock is a fixed frequency for all applications, in contrast to the ADC
sampling clock, the bunch-crossing clock is also used for operation of the I
2 C. This
enables the I
2 C to operate reliably at the highest speed supported by the GBT-SCA
of 1 MHz.
In the section of the digital design that handles readout from the buffer memories
and serialization of the data to the serial links, there is a need for a clock that is
a fixed fraction of the serial clock. This fraction must also be a factor of 10 since
the data is stored in 10-bit words, i.e. the clock needs to be either 1/10, 1/5, 1/2 or
1/1 of the serial clock speed. Since the buffer memories have a maximum operating
speed lower than the maximum serializing speed of 320 MHz, the full speed cannot
be chosen. Instead 1/2 of the serial speed is used due to the ease of generating a 1/2
clock from the input clock by halving, compared to using a 1/10 or a 1/5 clock, which
will require a counter based division, which is more prone to SEE as well. A lower
clock speed has the benefit of generating lower noise and power, but the circuitry
operating on this clock domain is of a small size and physically located furthest away
from the analogue section, so the influence is not significant.
In the section that handles writing to the buffer memory from each processing
channel, a higher clock speed is needed as well because in some cases there is a need
to store some control data at the same time as a sample is received. The same clock
is used in this section as for the output section, since with the output clock as 1/2 the
serializing clock it is always higher than two times the sample clock. This avoids a
separate clock domain, as would be the case if 1/10 or 1/5 would be selected.