42
3 SAMPA Chip Implementation
Serializers
Control
11
ADC
20 MSPS
Shaper
Shaping time control Gain control
IOs
CSA
R F
C F
32 channels
V REF+ V REF10bit
320Mbps
serial
links
Filters
Compression
Buffer
Digital
Fig. 3.1 Principal block diagram of the SAMPA
The charge-sensitive pre-amplifier integrates the input charge using a feedback
capacitor (C f ). The parallel large-ohmic transistor (R f ) is used to discharge the
capacitor, leading the signal back to the baseline level after the pulse with an exponential tail. Following the integration section is a pole-zero cancellation network to
remove undershoots in the pulse shape.
After that follows a pulse shaping element, which reduces the spectrum of the
signal resulting in a pulse with a 4th order semi-Gaussian shape. 4th order shaping is
chosen because it offers a faster return to baseline as compared to lower order filters.
This helps preventing pile-up effects when two or more pulses are closely spaced in
time.
The second stage of the shaper is a fully differential second order bridged-T filter
and includes a common-mode feedback network. The non-inverting stage adapts the
DC voltage level of the shaper output to use the full dynamic range of the ADC.
It consists of a parallel connection of two equally designed Miller compensated
amplifiers.
Some of the parameters can be set externally using static control pins. The gain
can be set to 20, 30 or 4 mV/fC, the shaping time can be set to either 160 or 300 ns,
and the signal input polarity can be chosen.
Biasing of the analogue block is done from a common internal configurable reference voltage source (band-gap) that creates the required 450, 600 and 750 mV
reference voltages. To be able to adjust the voltage reference, in case of large simulations versus production differences or to increase the yield, a 3-bit configuration is
provided through a digital configuration registers that can trim each of the voltages
±100 mV.
To reduce coupling of switching noise, the front-end has been separated into
three independent power domains. The CSA and first shaper share one power domain,
whereas the second shaper and the ADC have their own power domains. The separate
ground and power nets are not merged inside, but brought to the outside of the device
to individual pins such that it is up to the board designer to choose to externally
combine the nets in the way that is most suitable to reduce noise coupling further if
needed.
3 SAMPA Chip Implementation
Serializers
Control
11
ADC
20 MSPS
Shaper
Shaping time control Gain control
IOs
CSA
R F
C F
32 channels
V REF+ V REF10bit
320Mbps
serial
links
Filters
Compression
Buffer
Digital
Fig. 3.1 Principal block diagram of the SAMPA
The charge-sensitive pre-amplifier integrates the input charge using a feedback
capacitor (C f ). The parallel large-ohmic transistor (R f ) is used to discharge the
capacitor, leading the signal back to the baseline level after the pulse with an exponential tail. Following the integration section is a pole-zero cancellation network to
remove undershoots in the pulse shape.
After that follows a pulse shaping element, which reduces the spectrum of the
signal resulting in a pulse with a 4th order semi-Gaussian shape. 4th order shaping is
chosen because it offers a faster return to baseline as compared to lower order filters.
This helps preventing pile-up effects when two or more pulses are closely spaced in
time.
The second stage of the shaper is a fully differential second order bridged-T filter
and includes a common-mode feedback network. The non-inverting stage adapts the
DC voltage level of the shaper output to use the full dynamic range of the ADC.
It consists of a parallel connection of two equally designed Miller compensated
amplifiers.
Some of the parameters can be set externally using static control pins. The gain
can be set to 20, 30 or 4 mV/fC, the shaping time can be set to either 160 or 300 ns,
and the signal input polarity can be chosen.
Biasing of the analogue block is done from a common internal configurable reference voltage source (band-gap) that creates the required 450, 600 and 750 mV
reference voltages. To be able to adjust the voltage reference, in case of large simulations versus production differences or to increase the yield, a 3-bit configuration is
provided through a digital configuration registers that can trim each of the voltages
±100 mV.
To reduce coupling of switching noise, the front-end has been separated into
three independent power domains. The CSA and first shaper share one power domain,
whereas the second shaper and the ADC have their own power domains. The separate
ground and power nets are not merged inside, but brought to the outside of the device
to individual pins such that it is up to the board designer to choose to externally
combine the nets in the way that is most suitable to reduce noise coupling further if
needed.