Chapter 3
SAMPA Chip Implementation
This chapter gives a more in-depth description of the implementation of the design,
with a focus on the digital implementation. For a more in-depth description of the
analogue design, see [1].
3.1 Architectural Overview
The SAMPA chip consists of 32 identical channels, each containing a CSA, a shaper,
and an ADC, which together convert the input charge from the detector to a semiGaussian shape, and digitizes it with 10-bit precision. A block diagram is shown in
Fig. 3.1. The digital section is implemented as a single block receiving data from all of
the 32 ADCs. It contains a filtering, buffer, and compression-processing pipeline for
each of the input channel, in addition to providing common control and monitoring
solutions. Eleven serialization blocks interface with the buffers that are present at the
end of the channel filtering pipelines to transmit the data on to the receiving system.
The device is implemented in a 130 nm Taiwan Semiconductor Manufacturing Company (TSMC) Complementary Metal Oxide Semiconductor (CMOS) process where
the die measures 9.5 mm × 8.9 mm without cut lines. The die has 311 connectible
pads and is mounted in a 15 mm × 15 mm 320-pin Ball Grid Array (BGA) package.
3.1.1 Analogue Front-End
The front-end block consists of a positive/negative polarity CSA, a pole-zero cancellation network, a high pass filter, two bridged-T second order low pass filters and
a non-inverting stage [2], as shown in Fig. 3.2 [1].
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021
A. Velure, A Digital Signal Processor for Particle Detectors, Springer Theses,
https://doi.org/10.1007/978-3-030-71559-5_3
41
SAMPA Chip Implementation
This chapter gives a more in-depth description of the implementation of the design,
with a focus on the digital implementation. For a more in-depth description of the
analogue design, see [1].
3.1 Architectural Overview
The SAMPA chip consists of 32 identical channels, each containing a CSA, a shaper,
and an ADC, which together convert the input charge from the detector to a semiGaussian shape, and digitizes it with 10-bit precision. A block diagram is shown in
Fig. 3.1. The digital section is implemented as a single block receiving data from all of
the 32 ADCs. It contains a filtering, buffer, and compression-processing pipeline for
each of the input channel, in addition to providing common control and monitoring
solutions. Eleven serialization blocks interface with the buffers that are present at the
end of the channel filtering pipelines to transmit the data on to the receiving system.
The device is implemented in a 130 nm Taiwan Semiconductor Manufacturing Company (TSMC) Complementary Metal Oxide Semiconductor (CMOS) process where
the die measures 9.5 mm × 8.9 mm without cut lines. The die has 311 connectible
pads and is mounted in a 15 mm × 15 mm 320-pin Ball Grid Array (BGA) package.
3.1.1 Analogue Front-End
The front-end block consists of a positive/negative polarity CSA, a pole-zero cancellation network, a high pass filter, two bridged-T second order low pass filters and
a non-inverting stage [2], as shown in Fig. 3.2 [1].
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021
A. Velure, A Digital Signal Processor for Particle Detectors, Springer Theses,
https://doi.org/10.1007/978-3-030-71559-5_3
41