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Appendix B: Registers
Table B.7 Channel specific registers part 1
Register name
Address
Type
Default
Description
K1
[12:0]
0x00
RW
0x000
[12:0] First pole of the TCFU
K2
[12:0]
0x01
RW
0x000
[12:0] Second pole of the TCFU
K3
[12:0]
0x02
RW
0x000
[12:0] Third pole of the TCFU
K4
[12:0]
0x03
RW
0x000
[12:0] Fourth pole of the TCFU
L1
[12:0]
0x04
RW
0x000
[12:0] First zero of the TCFU
L2
[12:0]
0x05
RW
0x000
[12:0] Second zero of the TCFU
L3
[12:0]
0x06
RW
0x000
[12:0] Third zero of the TCFU
L4
[12:0]
0x07
RW
0x000
[12:0] Fourth zero of the TCFU
L30
[12:0]
0x08
RW
0x000
[12:0] TCFU IIR SOS first
zero(L3) gain
ZSTHR
[11:0]
0x09
RW
0x000
[11:0] Zero suppression threshold,
2 bit precision
ZSOFF
[12:0]
0x0A
RW
0x000
[12:0] Offset added before
truncation, 2’s compliment,
2 bit precision
ZSCFG
[8:0]
0x0B
RW
0x000
Zero suppression
configuration
RW
0x000
[1:0]
Glitch filter, minimum
accepted pulse, all, >1, >2,
>2
RW
0x000
[4:2]
Post-samples
RW
0x000
[6:5]
Pre-samples
RW
0x000
[7]
Change position of BC3 in
pipeline (BC3 after BC2)
RW
0x000
[8]
Enable Raw data output of
ZSU
FPD
[12:0]
0x0C
RW
0x000
[12:0] BC1 Fixed pedestal (offset
subtracted), 2’s compliment,
2 bit precision
VPD
[12:0]
0x0D
R
0x000
[12:0] BC1 variable pedestal, 2’s
compliment
BC2BSL
[12:0]
0x0E
R
0x000
[12:0] BC2 Computed Baseline, 2’s
compliment
BC3BSL
[12:0]
0x0F
R
0x000
[12:0] BC3 Computed Baseline, 2’s
compliment
PMDATA
[9:0]
0x10
RW
0x000
[9:0]
Data to be stored or read
from the pedestal memory
BC2LTHRREL [9:0]
0x11
RW
0x003
[9:0]
BC2 lower relative threshold
BC2HTHRREL [9:0]
0x12
RW
0x003
[9:0]
BC2 higher relative
threshold
BC2LTHRBSL [10:0]
0x13
RW
0x400
[10:0] BC2 lower saturation level
for baseline
(continued)