146
Appendix B: Registers
ERRORS The packet headers are equipped with a Hamming error correction code
which enables correction of one error and detection of two errors in the header.
The Hamming code is added to the header before it is written to the ring buffer
memory and it is checked again when it is read out of the ring buffer before it is
sent to the serial links. The ERRORS register contains a counter for the number
of errors found that could be corrected, and the number of errors that were not
correctable and where the packet was dropped. The counters collect errors from
all channel ring buffer outputs, in addition to the neighbouring ring buffer output
and the neighbouring input.
CMD:ERCLR (Error clear) Clears the errors in the ERRORS register.
BYPASS The BYPASS register controls a multiplexer situated directly at the serialOut[0] output. See Table B.6 for specifics.
0x1-0x3 Feed-through from one of the trigger inputs can be used for determining
round-trip delay of the system in a production environment. It can also be
used for qualifying the SLVS driver/receiver pair.
0x4 Feed-through from the neighbour input DinN can be used for bypassing
the device in the chain. This option also feeds NBflowstop_in to NBflowstop_out to enable full bypass of the device in daisy-chained mode.
0x5 Feed-through from delayed neighbour input after the neighbouring input
has passed through the delay specified by NBCFG[5:0]. This can be used
for qualifying the neighbour input delay chain. Also feeds NBflowstop_in
to NBflowstop_out for full bypass in a daisy chain.
0x6 Linear Feedback Shift Register (LFSR) generator is intended for use in
qualifying the SLVS driver. When selected it enables a 31 bit LFSR generator
which feeds back the XNOR of output 31 and 28. It runs at the serial link
clock.
0x7 The ADC test serializer selects the channel configured in the SERCHSEL
register and serializes it at the serial link half clock with a preamble of
b010011.
0x8-0xC Internal clock output can be used for qualifying the quality of the
clocks arriving from the clock divider. As there is a configurable delay chain
(ADCDEL) between the digital ADC clock and analogue ADC clock it is
possible to qualify the delay chain by providing an external ADC clock and
outputting the analogue ADC clock through this BYPASS mode.
0xD A ring oscillator has been implemented to determine process variations
and thermal/voltage effects. The oscillation is only operative after the
RINGOSCTST (Table B.3) command has been sent and then only for 256
ADC clock cycles or 512 oscillator cycles, whichever is the shortest. It should
oscillate at about 100.9 MHz for the worst case, 220 MHz for best case and
160.9 MHz for the typical case.
SERCHSEL (Serializer channel select) When BYPASS is set to 0x7, then this
selects the ADC channel used for the test serializer.
RINGCNT (Ring oscillator counter) In a non-test environment, it is possible to
determine the process speed of a device by comparing the ring oscillator clock
Appendix B: Registers
ERRORS The packet headers are equipped with a Hamming error correction code
which enables correction of one error and detection of two errors in the header.
The Hamming code is added to the header before it is written to the ring buffer
memory and it is checked again when it is read out of the ring buffer before it is
sent to the serial links. The ERRORS register contains a counter for the number
of errors found that could be corrected, and the number of errors that were not
correctable and where the packet was dropped. The counters collect errors from
all channel ring buffer outputs, in addition to the neighbouring ring buffer output
and the neighbouring input.
CMD:ERCLR (Error clear) Clears the errors in the ERRORS register.
BYPASS The BYPASS register controls a multiplexer situated directly at the serialOut[0] output. See Table B.6 for specifics.
0x1-0x3 Feed-through from one of the trigger inputs can be used for determining
round-trip delay of the system in a production environment. It can also be
used for qualifying the SLVS driver/receiver pair.
0x4 Feed-through from the neighbour input DinN can be used for bypassing
the device in the chain. This option also feeds NBflowstop_in to NBflowstop_out to enable full bypass of the device in daisy-chained mode.
0x5 Feed-through from delayed neighbour input after the neighbouring input
has passed through the delay specified by NBCFG[5:0]. This can be used
for qualifying the neighbour input delay chain. Also feeds NBflowstop_in
to NBflowstop_out for full bypass in a daisy chain.
0x6 Linear Feedback Shift Register (LFSR) generator is intended for use in
qualifying the SLVS driver. When selected it enables a 31 bit LFSR generator
which feeds back the XNOR of output 31 and 28. It runs at the serial link
clock.
0x7 The ADC test serializer selects the channel configured in the SERCHSEL
register and serializes it at the serial link half clock with a preamble of
b010011.
0x8-0xC Internal clock output can be used for qualifying the quality of the
clocks arriving from the clock divider. As there is a configurable delay chain
(ADCDEL) between the digital ADC clock and analogue ADC clock it is
possible to qualify the delay chain by providing an external ADC clock and
outputting the analogue ADC clock through this BYPASS mode.
0xD A ring oscillator has been implemented to determine process variations
and thermal/voltage effects. The oscillation is only operative after the
RINGOSCTST (Table B.3) command has been sent and then only for 256
ADC clock cycles or 512 oscillator cycles, whichever is the shortest. It should
oscillate at about 100.9 MHz for the worst case, 220 MHz for best case and
160.9 MHz for the typical case.
SERCHSEL (Serializer channel select) When BYPASS is set to 0x7, then this
selects the ADC channel used for the test serializer.
RINGCNT (Ring oscillator counter) In a non-test environment, it is possible to
determine the process speed of a device by comparing the ring oscillator clock