140
Appendix B: Registers
configurable delay is 192 samples which correspond to 19.2 µs when running at
an ADC clock of 10 MHz. The delay is inserted at the entry of the digital design
before any data handling or compression happens. The configuration does not
alter the length of the time window, but merely moves the trigger point in the
sample stream earlier in time than when the trigger was received.
TWLENL, TWLENH (Time window length) The number of cycles +1 that a
time window will last from a trigger start. In continuous mode, this will impact
the average length of packets.
ACQSTARTL, ACQSTARTH (Acquisition start) The number of cycles from
the start of a trigger that will be suppressed in the output data when running in
zero-suppressed mode or cluster sum mode. It is useful for instance in cases where
it is known that there always will be an unwanted signal perturbation directly after
the trigger which could badly influence the filters. Set the value to 0 to disable.
ACQENDL, ACQEND (Acquisition end) The number of cycles from the start
of trigger to when sample acquisition should end. The remaining samples after
this point, until the end of the time window, will be suppressed when operating
in zero suppression mode or cluster sum mode. If the value is set higher or equal
to TWLEN then it has no effect. The boolean equation is acquisition_enable =
(T W L E N >= AC Q ST ART )&(T W L E N <= AC Q E N D).
VACFG[0] Continuous mode enable Enables automatic generation of a new
trigger at the end of a time window. A manual soft or pin trigger would prematurely end the current time window and start a new one. Manual pin triggering
can be used to align time windows across multiple SAMPAs since they will all
start at the same time.
CMD:TRCLR (Trigger clear) Clears the trigger counter TRCNT.
CMD:SWTRG (Software trigger) Provides a single soft trigger, mainly for test
purposes.
CMD:BXCLR (Bunch crossing clear) Clears the bunch crossing counter
BXCNT.
CHENx (Channel enable) Provides the possibility to shut down specific channels
to avoid that they send data. It works by disabling all the filters and suppressing
the data readout for the channel in addition to disabling the clock for the ADC.
B.1.3 Channel Register Access
The register layout has been designed to minimize the number of writes needed
to update the channel registers and pedestal memories of each channel. By using
the I
2 C automatic address increment feature, it is possible to complete all writes
needed to update one channel or pedestal address in one continuous I
2 C command.
An additional broadcast bit can be set to write the same data to all channels so that
individual access is not needed. When filling the pedestal memory it is possible to
set the pedestal memory to increment on each write avoiding the need to update the
two registers each time.
Appendix B: Registers
configurable delay is 192 samples which correspond to 19.2 µs when running at
an ADC clock of 10 MHz. The delay is inserted at the entry of the digital design
before any data handling or compression happens. The configuration does not
alter the length of the time window, but merely moves the trigger point in the
sample stream earlier in time than when the trigger was received.
TWLENL, TWLENH (Time window length) The number of cycles +1 that a
time window will last from a trigger start. In continuous mode, this will impact
the average length of packets.
ACQSTARTL, ACQSTARTH (Acquisition start) The number of cycles from
the start of a trigger that will be suppressed in the output data when running in
zero-suppressed mode or cluster sum mode. It is useful for instance in cases where
it is known that there always will be an unwanted signal perturbation directly after
the trigger which could badly influence the filters. Set the value to 0 to disable.
ACQENDL, ACQEND (Acquisition end) The number of cycles from the start
of trigger to when sample acquisition should end. The remaining samples after
this point, until the end of the time window, will be suppressed when operating
in zero suppression mode or cluster sum mode. If the value is set higher or equal
to TWLEN then it has no effect. The boolean equation is acquisition_enable =
(T W L E N >= AC Q ST ART )&(T W L E N <= AC Q E N D).
VACFG[0] Continuous mode enable Enables automatic generation of a new
trigger at the end of a time window. A manual soft or pin trigger would prematurely end the current time window and start a new one. Manual pin triggering
can be used to align time windows across multiple SAMPAs since they will all
start at the same time.
CMD:TRCLR (Trigger clear) Clears the trigger counter TRCNT.
CMD:SWTRG (Software trigger) Provides a single soft trigger, mainly for test
purposes.
CMD:BXCLR (Bunch crossing clear) Clears the bunch crossing counter
BXCNT.
CHENx (Channel enable) Provides the possibility to shut down specific channels
to avoid that they send data. It works by disabling all the filters and suppressing
the data readout for the channel in addition to disabling the clock for the ADC.
B.1.3 Channel Register Access
The register layout has been designed to minimize the number of writes needed
to update the channel registers and pedestal memories of each channel. By using
the I
2 C automatic address increment feature, it is possible to complete all writes
needed to update one channel or pedestal address in one continuous I
2 C command.
An additional broadcast bit can be set to write the same data to all channels so that
individual access is not needed. When filling the pedestal memory it is possible to
set the pedestal memory to increment on each write avoiding the need to update the
two registers each time.