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Appendix B: Registers
Table B.1 Global registers part 1
Register name
Address
Type
Default
Description
HWADD
[3:0]
0x00
R
0x00
[3:0]
Chip address (hardware
address)
TRCNTL
[7:0]
0x01
R
0x00
[7:0]
Trigger count, lower byte
TRCNTH
[7:0]
0x02
R
0x00
[7:0]
Trigger count, upper byte
BXCNTLL
[7:0]
0x03
R
0x00
[7:0]
Bunch crossing count,
lower byte
BXCNTLH
[7:0]
0x04
R
0x00
[7:0]
Bunch crossing count, mid
byte
BXCNTHL
[3:0]
0x05
R
0x00
[3:0]
Bunch crossing count,
upper byte
PRETRG
[7:0]
0x06
RW
0x00
[7:0]
Number of pre-samples
(Pre-trigger delay), max
192
TWLENL
[7:0]
0x07
RW
0xE7
[7:0]
Number of cycles for time
window +1, lower byte
TWLENH
[1:0]
0x08
RW
0x03
[1:0]
Number of cycles for time
window +1, upper byte
ACQSTARTL [7:0]
0x09
RW
0x00
[7:0]
Number of cycles to wait
before acquisition starts,
lower byte
ACQSTARTH [1:0]
0x0A
RW
0x00
[1:0]
Number of cycles to wait
before acquisition starts,
upper byte
ACQENDL
[7:0]
0x0B
RW
0xFF
[7:0]
Number of cycles elapsed
from trigger to acquisition
end +1, lower byte
ACQENDH
[1:0]
0x0C
RW
0x03
[1:0]
Number of cycles elapsed
from trigger to acquisition
end +1, upper byte
VACFG
[7:0]
0x0D
RW
0x30
Various configuration
settings
RW
0x00
[0]
Continuous mode enabled
RW
0x00
[1]
Raw data enable
RW
0x00
[2]
Cluster sum enable
RW
0x00
[3]
Huffman enable
RW
0x01
[4]
Enable header generation
for empty channels
RW
0x01
[5]
Power save enable
RW
0x00
[6]
Enable automatic clock
gating on I 2 C block
RW
0x00
[7]
Enable clock gating on
neighbour block when
number of neighbour is 0
CMD
[2:0]
0x0E
RW
0x00
[2:0]
Commands, see Table B.3
(continued)