4.3 Validation and Testing
115
Fig. 4.7 Overview of the processing chain of the first prototype of the SAMPA digital section
including debug facilities (yellow)
checker for the built-in memory test in the DAQ system FPGA firmware had a bug
at the time of testing and therefore did not report any errors. Additionally, 4% of
the devices showed non-working analogue channels, 3% had abnormally high power
consumption or shorts, and 39% had an issue with the analogue bias reference where
the voltage was out of specification. The voltage bias issues can be remedied by
using an external circuitry and is therefore of less concern. The total yield for the
first batch is 44% if all issues are included, or 81% if the bias reference problems is
not considered. Only the value of the baseline was used for determining if a channel
was broken when testing the first batch, so more broken channels might possibly
have been detected if the channels had been tested with an input signal.
For the second batch, 748 devices were tested.
6 6% of the devices produced an
error during scan chain testing, 0.3% had a pin error from the JTAG testing, 6% gave
an error from the memory testing and 0.9% gave both a scan chain error as well
as a memory error. Additionally, 10% of the devices had analogue channel issues,
1.3% had abnormally high power consumption or shorts, and 37% had an issue with
the analogue bias reference where the voltage was out of specification. Additionally,
there were 2.5% with unspecified issues, which could not be attributed to either of
the above issues. Overall, the total yield for the second batch is 34% if all issues are
included, or 72% if the devices with only bias reference problems are counted as
good devices as well.
Since the on-chip memory occupies almost half the area in the device, it is natural
that there could be about the same amount of errors in the memory as in the logic
itself, as seen in the testing of the second batch. The percentage of devices with both
errors is also on par with what would be expected. If this reasoning is applied to
the yield for the first batch, the yield for both batches would be the same, which
indicates that the testing is consistent and that the scan chain and memory tester are
both functioning correctly.
6 Test of second batch was performed by Anders Oskarsson and David Silvermyr, Lund University,
Sweden.
115
Fig. 4.7 Overview of the processing chain of the first prototype of the SAMPA digital section
including debug facilities (yellow)
checker for the built-in memory test in the DAQ system FPGA firmware had a bug
at the time of testing and therefore did not report any errors. Additionally, 4% of
the devices showed non-working analogue channels, 3% had abnormally high power
consumption or shorts, and 39% had an issue with the analogue bias reference where
the voltage was out of specification. The voltage bias issues can be remedied by
using an external circuitry and is therefore of less concern. The total yield for the
first batch is 44% if all issues are included, or 81% if the bias reference problems is
not considered. Only the value of the baseline was used for determining if a channel
was broken when testing the first batch, so more broken channels might possibly
have been detected if the channels had been tested with an input signal.
For the second batch, 748 devices were tested.
6 6% of the devices produced an
error during scan chain testing, 0.3% had a pin error from the JTAG testing, 6% gave
an error from the memory testing and 0.9% gave both a scan chain error as well
as a memory error. Additionally, 10% of the devices had analogue channel issues,
1.3% had abnormally high power consumption or shorts, and 37% had an issue with
the analogue bias reference where the voltage was out of specification. Additionally,
there were 2.5% with unspecified issues, which could not be attributed to either of
the above issues. Overall, the total yield for the second batch is 34% if all issues are
included, or 72% if the devices with only bias reference problems are counted as
good devices as well.
Since the on-chip memory occupies almost half the area in the device, it is natural
that there could be about the same amount of errors in the memory as in the logic
itself, as seen in the testing of the second batch. The percentage of devices with both
errors is also on par with what would be expected. If this reasoning is applied to
the yield for the first batch, the yield for both batches would be the same, which
indicates that the testing is consistent and that the scan chain and memory tester are
both functioning correctly.
6 Test of second batch was performed by Anders Oskarsson and David Silvermyr, Lund University,
Sweden.