114
4 Verification and Testing
not achieved unless fitting was used to get the amplitude and shaping time of the
received pulses.
Originally, the issue was thought to be due to metastability in the sample value
when it was transferred between the ADC and the digital section since the two
sections had separate input clocks. But, by supplying a delayed clock to the ADC,
that was in sync with the digital clock, it could be seen that this was not the cause as
the signal quality could not be improved. Further tests on the separate ADC prototype
showed that the SAR state machine was missing an output register so data was only
valid for a few nanoseconds after the end of a conversion. In the design of the second
prototype, the missing registers were added and the ADC was supplied with both
the sampling clock and the SAR state machine clock from the digital part to avoid
any metastability issues. AMS simulations were additionally completed to avoid any
other possible analogue-digital issues for the next prototype.
To avoid that a possible error in the digital design would prevent the testing of
the performance of the combined analogue, ADC and digital design, some external
test pins were included, as shown in Fig. 4.7. Separate bypass signals were added for
each filter block, in case the filter failed to work or in case the slow control interface
did not operate properly, which would prevent the filters from being configured. A
parallel output was also added so that the signals at the output of each filter block
for one of the channels could be analysed. The parallel output could also be used
to output the raw data from each of the ADCs in case some parts of the memory or
serialization block failed to work. As the data on the parallel output was registered on
the digital side before exiting, it was not possible to observe the ADC signals directly
as on the separate ADC prototype. A parallel input data port was also present to feed
the digital data chain directly in case the ADC would not operate properly.
Through the use of the parallel test input, a test signal could be applied and
verified on the serial output. This proved the proper operation of the continuous
triggering mode and the digital signal processing chain together with the ring buffer
and serializing. The slow control, which was not I
2 C at the time, but a custom serial
protocol, was proven to work correctly by reading and writing all available registers.
The filters were not extensively tested, as they were not significantly altered from
the S-ALTRO implementation.
4.3.2 Test Results for SAMPA V2
The following section presents the results for the second prototype that contained
the full-chip design, received summer 2016.
4.3.2.1 Manufacturing Defects
For the first batch of 142 tested devices, it was found that 10% of the devices produced
an error during scan chain testing and no devices had JTAG errors. However, the
4 Verification and Testing
not achieved unless fitting was used to get the amplitude and shaping time of the
received pulses.
Originally, the issue was thought to be due to metastability in the sample value
when it was transferred between the ADC and the digital section since the two
sections had separate input clocks. But, by supplying a delayed clock to the ADC,
that was in sync with the digital clock, it could be seen that this was not the cause as
the signal quality could not be improved. Further tests on the separate ADC prototype
showed that the SAR state machine was missing an output register so data was only
valid for a few nanoseconds after the end of a conversion. In the design of the second
prototype, the missing registers were added and the ADC was supplied with both
the sampling clock and the SAR state machine clock from the digital part to avoid
any metastability issues. AMS simulations were additionally completed to avoid any
other possible analogue-digital issues for the next prototype.
To avoid that a possible error in the digital design would prevent the testing of
the performance of the combined analogue, ADC and digital design, some external
test pins were included, as shown in Fig. 4.7. Separate bypass signals were added for
each filter block, in case the filter failed to work or in case the slow control interface
did not operate properly, which would prevent the filters from being configured. A
parallel output was also added so that the signals at the output of each filter block
for one of the channels could be analysed. The parallel output could also be used
to output the raw data from each of the ADCs in case some parts of the memory or
serialization block failed to work. As the data on the parallel output was registered on
the digital side before exiting, it was not possible to observe the ADC signals directly
as on the separate ADC prototype. A parallel input data port was also present to feed
the digital data chain directly in case the ADC would not operate properly.
Through the use of the parallel test input, a test signal could be applied and
verified on the serial output. This proved the proper operation of the continuous
triggering mode and the digital signal processing chain together with the ring buffer
and serializing. The slow control, which was not I
2 C at the time, but a custom serial
protocol, was proven to work correctly by reading and writing all available registers.
The filters were not extensively tested, as they were not significantly altered from
the S-ALTRO implementation.
4.3.2 Test Results for SAMPA V2
The following section presents the results for the second prototype that contained
the full-chip design, received summer 2016.
4.3.2.1 Manufacturing Defects
For the first batch of 142 tested devices, it was found that 10% of the devices produced
an error during scan chain testing and no devices had JTAG errors. However, the