4.2 Hardware Verification of the Digital Design
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and the analysis program. The emulator is primarily useful to verify the correct
decompression of the various types of compression, the correct handling of bad or
incomplete packets, verifying the correct decoding of SAMPA headers and checking
that the analysis program can support the necessary bandwidth.
4.3 Validation and Testing
Three prototype production runs have been completed of the SAMPA design. The
first prototype run contained three test chips. The first of which was a three-channel
CSA + shaper, the second contained a single ADC and an SLVS driver/receiver
pair, and the third was a reduced version of the complete design with only three full
front-end channels with ADCs and a simplified digital section.
The second prototype run contained the complete 32-channel design in addition
to three test chips. Since the full design does not have provision for either injecting
or reading signals along the analogue processing chain, it becomes difficult to debug
or verify the performance of the individual parts by themselves. For instance, the
ADC does not have enough resolution to determine the analogue noise level to a
satisfactory degree at low gains. The sampling speed is also too low to investigate
the pulse shape of the analogue signal. To determine the Effective Number Of Bits
(ENOB) of an ADC the common technique is to inject a full range sine wave into the
input of the ADC. This is not possible in this context since the input signal passes
through pulse shaping elements. An analogue-only test chip, which only contained
the 32 CSA + shaper, has therefore been added to verify the analogue performance.
The full 32 channels are included to investigate any issues on power distribution
and crosstalk. Additionally, a chip containing a stand-alone ADC block is included
to verify the ADC performance and another chip for the SLVS driver/receiver pair.
The full chip was mounted in a 15 × 15 mm 372-ball BGA package, identical to the
final package to be used for the production run. This chip was also available as a
wire-bonded version. The other test chips were all wire-bonded.
More information on the test of the first prototype can be found in [27] for the
analogue and ADC, and in [28] for the three channel simplified design and in [29]
for the second prototype.
The test environment described in the previous section was used for verification
of both the ADC and digital version of the first prototype and the complete design
for the second and third prototype.
4.3.1 Test Results for SAMPA V1
Due to a design issue that caused inconsistencies in the data received by the digital
section from the ADC, the analogue performance of the first full-chip prototype was
not tested extensively. Some analysis is available in [28], but suitable results were
113
and the analysis program. The emulator is primarily useful to verify the correct
decompression of the various types of compression, the correct handling of bad or
incomplete packets, verifying the correct decoding of SAMPA headers and checking
that the analysis program can support the necessary bandwidth.
4.3 Validation and Testing
Three prototype production runs have been completed of the SAMPA design. The
first prototype run contained three test chips. The first of which was a three-channel
CSA + shaper, the second contained a single ADC and an SLVS driver/receiver
pair, and the third was a reduced version of the complete design with only three full
front-end channels with ADCs and a simplified digital section.
The second prototype run contained the complete 32-channel design in addition
to three test chips. Since the full design does not have provision for either injecting
or reading signals along the analogue processing chain, it becomes difficult to debug
or verify the performance of the individual parts by themselves. For instance, the
ADC does not have enough resolution to determine the analogue noise level to a
satisfactory degree at low gains. The sampling speed is also too low to investigate
the pulse shape of the analogue signal. To determine the Effective Number Of Bits
(ENOB) of an ADC the common technique is to inject a full range sine wave into the
input of the ADC. This is not possible in this context since the input signal passes
through pulse shaping elements. An analogue-only test chip, which only contained
the 32 CSA + shaper, has therefore been added to verify the analogue performance.
The full 32 channels are included to investigate any issues on power distribution
and crosstalk. Additionally, a chip containing a stand-alone ADC block is included
to verify the ADC performance and another chip for the SLVS driver/receiver pair.
The full chip was mounted in a 15 × 15 mm 372-ball BGA package, identical to the
final package to be used for the production run. This chip was also available as a
wire-bonded version. The other test chips were all wire-bonded.
More information on the test of the first prototype can be found in [27] for the
analogue and ADC, and in [28] for the three channel simplified design and in [29]
for the second prototype.
The test environment described in the previous section was used for verification
of both the ADC and digital version of the first prototype and the complete design
for the second and third prototype.
4.3.1 Test Results for SAMPA V1
Due to a design issue that caused inconsistencies in the data received by the digital
section from the ADC, the analogue performance of the first full-chip prototype was
not tested extensively. Some analysis is available in [28], but suitable results were