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4 Verification and Testing
for irradiation tests, were there is a need to count the number of errors encountered,
this was implemented in the FPGA firmware, since the pulses generated by the tester
are faster than what can be detected from software and therefore needs to be sampled
by the FPGA.
4.2.4 DAQ Verification and FPGA Prototyping
Testing of the complete readout chain in a simulation is difficult due to the complex
interaction between the SAMPA, the FPGA firmware, the ARM processor in the
FPGA, the Linux system and the control and analysis software on the computer.
The FPGA firmware can by itself be verified through simulation by reusing the toplevel testbench used for verification of the SAMPA and combining it with testbench
functions, which verifies that the FPGA firmware can de-serialize and aggregated
correctly into memory.
To verify the full readout chain, the Verilog code for the digital part of the SAMPA
was made synthesizable for the Altera FPGA and synthesized into the top level of the
FPGA code. While running the system, selecting between communicating with the
external SAMPA and the synthesized internal SAMPA can be done through a switch.
For the first prototype, the full SAMPA was synthesized for use in the FPGA, while
for the second prototype a reduced version of the design with only eight channels
was used. The SAMPA design utilizes several large multiplexer structures, which
prohibits the full design to fit on the utilized FPGA.
The only modifications necessary to make the SAMPA code synthesizable on the
FPGA was to modify the TSMC cell library so that custom cells were replaced by
normal cells. Additionally, the FPGA synthesizer was told to use memories based
on registers instead of the original SRAM IP memory. For efficiency, the synthesizer
automatically infers block memory when large register-based memories are found.
The option to use register-based memory was already defined in the original code as
it is utilized for running faster simulations during debugging of testbenches. Features
that rely on the specific delay of cells were not taken into consideration during the
conversion i.e. neighbour input delay compensation, ADC clock delay compensation
and the ring oscillator. If these features were required, they could have been adapted
to use the vendor provided delay cells of the FPGA.
To be able to verify that the connections between the DAQ board and the mezzanine board containing the SAMPA were valid before the SAMPA and mezzanine
boards were produced, the synthesized SAMPA digital code was implemented on a
separate FPGA board and the two boards were interconnected through a cable. This
allowed operation of the complete DAQ system readout chain as if all components
were available.
An emulator of the DAQ functionality, that replicates the packets coming from
the DAQ board, was made to aid in developing and verifying the functionality of
the analysis program. The program can be run locally on the computer or directly
on the Linux system of the DAQ board to verify the connection between the board
4 Verification and Testing
for irradiation tests, were there is a need to count the number of errors encountered,
this was implemented in the FPGA firmware, since the pulses generated by the tester
are faster than what can be detected from software and therefore needs to be sampled
by the FPGA.
4.2.4 DAQ Verification and FPGA Prototyping
Testing of the complete readout chain in a simulation is difficult due to the complex
interaction between the SAMPA, the FPGA firmware, the ARM processor in the
FPGA, the Linux system and the control and analysis software on the computer.
The FPGA firmware can by itself be verified through simulation by reusing the toplevel testbench used for verification of the SAMPA and combining it with testbench
functions, which verifies that the FPGA firmware can de-serialize and aggregated
correctly into memory.
To verify the full readout chain, the Verilog code for the digital part of the SAMPA
was made synthesizable for the Altera FPGA and synthesized into the top level of the
FPGA code. While running the system, selecting between communicating with the
external SAMPA and the synthesized internal SAMPA can be done through a switch.
For the first prototype, the full SAMPA was synthesized for use in the FPGA, while
for the second prototype a reduced version of the design with only eight channels
was used. The SAMPA design utilizes several large multiplexer structures, which
prohibits the full design to fit on the utilized FPGA.
The only modifications necessary to make the SAMPA code synthesizable on the
FPGA was to modify the TSMC cell library so that custom cells were replaced by
normal cells. Additionally, the FPGA synthesizer was told to use memories based
on registers instead of the original SRAM IP memory. For efficiency, the synthesizer
automatically infers block memory when large register-based memories are found.
The option to use register-based memory was already defined in the original code as
it is utilized for running faster simulations during debugging of testbenches. Features
that rely on the specific delay of cells were not taken into consideration during the
conversion i.e. neighbour input delay compensation, ADC clock delay compensation
and the ring oscillator. If these features were required, they could have been adapted
to use the vendor provided delay cells of the FPGA.
To be able to verify that the connections between the DAQ board and the mezzanine board containing the SAMPA were valid before the SAMPA and mezzanine
boards were produced, the synthesized SAMPA digital code was implemented on a
separate FPGA board and the two boards were interconnected through a cable. This
allowed operation of the complete DAQ system readout chain as if all components
were available.
An emulator of the DAQ functionality, that replicates the packets coming from
the DAQ board, was made to aid in developing and verifying the functionality of
the analysis program. The program can be run locally on the computer or directly
on the Linux system of the DAQ board to verify the connection between the board