4.2 Hardware Verification of the Digital Design
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access to changing the frequency of the clocks supplied to the SAMPA as well as
custom test and control features for radiation testing, digital verification and mass
testing.
4.2.2.2 SAMPA Analyser
Data handling on the computer is taken care of by a graphical ROOT program. The
program sets up the Ethernet connection with the FPGA board and receives data
packets. The integrity of the packets is verified through the parity and Hamming
codes present in the packet headers. Heuristic methods are additionally employed to
detect anomalies in the packet coding. By decoding the run length encoding of the
compression and checking that uncompressed data is not larger than the maximum
time window length of 1024, the validity of the compression can also be confirmed.
The sampled signals are plotted and displayed per channel, the raw data packets
are additionally written to a ROOT file for further analysis off-line. When running
in continuous acquisition mode, the plots can be set to update only when the data
passes a threshold value, similar to the triggering function on an oscilloscope. For
each channel, both the waveform of the last acquired time window, a histogram of all
samples and a histogram of the maximum value per time window is presented. The
full histogram can be used for determining the noise level, whereas the max value
histogram can be used to determine the amplitude of an injected pulse. Fitting of a
4th order Gaussian shape can be applied to pulses in the waveform display to get the
shaping time and amplitude of the received pulse.
4.2.3 Design for Test Features
For design simplicity, both the JTAG and scan-chain tests are implemented in software and the control signals are bit-banged through interfacing with the Command
and Control module on the FPGA. The JTAG tester is implemented directly in the
SAMPA Communicator program and runs walking one and walking zero patterns
across the input/output pins of the SAMPA to detect stuck pins, inverted pins, or
shorts. The scan chain tester is, on the other hand, implemented as a program running on the embedded Linux system. This is done to save on testing time by avoiding
to pass data through the slow UART-to-bus interface. Running directly on the Linux
system provides a maximum speed close to 1 MHz compared to a few kHz when
running from the computer. The scan chain program is a port of the Verilog testbench, discussed in Sect. 4.1.3.1, into C and uses the same test-vector files as used
by the testbench [26].
5 The tester for the built-in memory tester could also have been
implemented in software for the manufacturing defect tests, as the SAMPA has a
go/no-go output to indicate if there is an error. However, to be able to reuse the tester
5 Testbench conversion done by Bruno Sanches, University of São Paulo, Brazil.
111
access to changing the frequency of the clocks supplied to the SAMPA as well as
custom test and control features for radiation testing, digital verification and mass
testing.
4.2.2.2 SAMPA Analyser
Data handling on the computer is taken care of by a graphical ROOT program. The
program sets up the Ethernet connection with the FPGA board and receives data
packets. The integrity of the packets is verified through the parity and Hamming
codes present in the packet headers. Heuristic methods are additionally employed to
detect anomalies in the packet coding. By decoding the run length encoding of the
compression and checking that uncompressed data is not larger than the maximum
time window length of 1024, the validity of the compression can also be confirmed.
The sampled signals are plotted and displayed per channel, the raw data packets
are additionally written to a ROOT file for further analysis off-line. When running
in continuous acquisition mode, the plots can be set to update only when the data
passes a threshold value, similar to the triggering function on an oscilloscope. For
each channel, both the waveform of the last acquired time window, a histogram of all
samples and a histogram of the maximum value per time window is presented. The
full histogram can be used for determining the noise level, whereas the max value
histogram can be used to determine the amplitude of an injected pulse. Fitting of a
4th order Gaussian shape can be applied to pulses in the waveform display to get the
shaping time and amplitude of the received pulse.
4.2.3 Design for Test Features
For design simplicity, both the JTAG and scan-chain tests are implemented in software and the control signals are bit-banged through interfacing with the Command
and Control module on the FPGA. The JTAG tester is implemented directly in the
SAMPA Communicator program and runs walking one and walking zero patterns
across the input/output pins of the SAMPA to detect stuck pins, inverted pins, or
shorts. The scan chain tester is, on the other hand, implemented as a program running on the embedded Linux system. This is done to save on testing time by avoiding
to pass data through the slow UART-to-bus interface. Running directly on the Linux
system provides a maximum speed close to 1 MHz compared to a few kHz when
running from the computer. The scan chain program is a port of the Verilog testbench, discussed in Sect. 4.1.3.1, into C and uses the same test-vector files as used
by the testbench [26].
5 The tester for the built-in memory tester could also have been
implemented in software for the manufacturing defect tests, as the SAMPA has a
go/no-go output to indicate if there is an error. However, to be able to reuse the tester
5 Testbench conversion done by Bruno Sanches, University of São Paulo, Brazil.