4.1 Functional Verification of the Digital Design
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Data Format.
Unit
Checker
Monitor
Sequencer
Ring buffer
Driver
(a) DFU and Ring buffer
Heartbeat
gen.
Sync
gen.
Channel data
gen.
Serial out
Neighbour
input
Neighbour
ring buffer
Checker
Checker
Link data
generator
Sequencer
Slave chip
Master chip
(b) Daisy chain
Fig. 4.2 Module based testbenches. Grey boxes are modules from the design
An effort was put in to increase the coverage of the design for v3. In v2, the lower
coverage was mostly caused by dead or unreachable code branches that were removed
for v3. In other cases, it was found that not all bits in a register had been transitioned
during the testing to cover all parts of the design. In v2, the data-formatting unit and
ring buffer were only verified on the top level and so the coverage numbers are not
included.
4.1.3 System Level Testing
The testbench for the top-level design is sketched in Fig. 4.3. The testbench can
be set up for testing of a single SAMPA or for testing of two SAMPAs in daisychained mode by changing a parameter at compile time. When testing only a single