98
4 Verification and Testing
For interfacing to some of the DUTs, Bus Functional Models (BFMs) have been
created, which abstract the multi-cycle interfacing to the module into a single call
to make the testbench sequences both easier to write and read. This was done for
the JTAG testbench as well as the I
2 C testbench. The JTAG module deviates from
the general testbench in Fig. 4.1a by an additional possibility to connect two JTAG
modules together to verify that JTAG chaining works. The I
2 C module deviates in
that it interfaces to a generic wishbone attached memory and can be driven from both
the I
2 C BFM and a module containing the I
2 C master from the GBT-SCA project, the
same device as will be used in the experiment. A separate BFM is used to interface
with the GBT-SCA master I
2 C unit. In this way, the compatibility with the GBT-SCA
can be verified before the chip is produced.
The testbenches that verify parts of the data-formatting unit and ring buffer are
more complex as they need to model more of the surrounding circuitry. For the Huffman testbench shown in Fig. 4.1b, the sequencer generates sample data that is sent to
the Huffman DUT and the Huffman model. The model stores the compressed data in
a memory array and this data is used to compare against the output of the Huffman
DUT by an independent checker process. An event generator model controlled by
the sequencer generates the necessary signals to simulate events with varying length
and spacing. The output of the data-formatting unit is fed into a model of the ring
buffer and a checker verifies the data in the memory against the data produced by
the Huffman model earlier.
The testbench shown in Fig. 4.2a takes a slightly different approach as it is based on
the SystemVerilog method of designing testbenches with a separate driver, monitor,
sequencer, and checker.
1 The driver generates both the stimuli and models the two
DUTs. The monitor models the memory readout behaviour and provides the data to
the checker, which verifies it against the model data.
The daisy chaining testbench was built in two steps. In the first step, the data from
the neighbouring chip was generated by a model (link data generator in Fig. 4.2b). As
the daisy chaining is supposed to pass the data verbatim, except for the suppression of
sync packets, there is no need to model the behaviour of the DUTs, and a FIFO buffer
is used instead. A checker is present at both the interface between the neighbour input
module and the ring buffer, as well as on the output of the ring buffer. For v3, the
RTL code for the serial output module, the heartbeat generator, and sync generator
was added to verify that all inter-delays between the communication of the master
and slave unit had been taken into account in the model.
The coverage for the tested modules is listed in Tabel 4.1 for both v2 and v3.
The coverage numbers were generated by Mentor Questa Sim [3]. The coverage
number includes both statement coverage, branch coverage, condition coverage, and
toggle coverage. Statement coverage verifies that each code line is hit at least once.
Branch coverage checks that each branch of an if/else or conditional operator is hit
once. Condition coverage sees that all combinations of the input terms of a branch
statement are covered. Toggle coverage verifies that each bit of each register or wire
has transitioned from 0 to 1 and opposite at least once.
1 DFU ring buffer testbench created by Raul Acosta Hernandez, University of São Paulo, Brazil.
4 Verification and Testing
For interfacing to some of the DUTs, Bus Functional Models (BFMs) have been
created, which abstract the multi-cycle interfacing to the module into a single call
to make the testbench sequences both easier to write and read. This was done for
the JTAG testbench as well as the I
2 C testbench. The JTAG module deviates from
the general testbench in Fig. 4.1a by an additional possibility to connect two JTAG
modules together to verify that JTAG chaining works. The I
2 C module deviates in
that it interfaces to a generic wishbone attached memory and can be driven from both
the I
2 C BFM and a module containing the I
2 C master from the GBT-SCA project, the
same device as will be used in the experiment. A separate BFM is used to interface
with the GBT-SCA master I
2 C unit. In this way, the compatibility with the GBT-SCA
can be verified before the chip is produced.
The testbenches that verify parts of the data-formatting unit and ring buffer are
more complex as they need to model more of the surrounding circuitry. For the Huffman testbench shown in Fig. 4.1b, the sequencer generates sample data that is sent to
the Huffman DUT and the Huffman model. The model stores the compressed data in
a memory array and this data is used to compare against the output of the Huffman
DUT by an independent checker process. An event generator model controlled by
the sequencer generates the necessary signals to simulate events with varying length
and spacing. The output of the data-formatting unit is fed into a model of the ring
buffer and a checker verifies the data in the memory against the data produced by
the Huffman model earlier.
The testbench shown in Fig. 4.2a takes a slightly different approach as it is based on
the SystemVerilog method of designing testbenches with a separate driver, monitor,
sequencer, and checker.
1 The driver generates both the stimuli and models the two
DUTs. The monitor models the memory readout behaviour and provides the data to
the checker, which verifies it against the model data.
The daisy chaining testbench was built in two steps. In the first step, the data from
the neighbouring chip was generated by a model (link data generator in Fig. 4.2b). As
the daisy chaining is supposed to pass the data verbatim, except for the suppression of
sync packets, there is no need to model the behaviour of the DUTs, and a FIFO buffer
is used instead. A checker is present at both the interface between the neighbour input
module and the ring buffer, as well as on the output of the ring buffer. For v3, the
RTL code for the serial output module, the heartbeat generator, and sync generator
was added to verify that all inter-delays between the communication of the master
and slave unit had been taken into account in the model.
The coverage for the tested modules is listed in Tabel 4.1 for both v2 and v3.
The coverage numbers were generated by Mentor Questa Sim [3]. The coverage
number includes both statement coverage, branch coverage, condition coverage, and
toggle coverage. Statement coverage verifies that each code line is hit at least once.
Branch coverage checks that each branch of an if/else or conditional operator is hit
once. Condition coverage sees that all combinations of the input terms of a branch
statement are covered. Toggle coverage verifies that each bit of each register or wire
has transitioned from 0 to 1 and opposite at least once.
1 DFU ring buffer testbench created by Raul Acosta Hernandez, University of São Paulo, Brazil.