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14. C. E. Cummings, “Simulation and synthesis techniques for asynchronous FIFO design with
asynchronous pointer comparisons,” in Synopsis User Group Meeting, 2002.
15. ARM. (2017) Single port and dual port SRAM embedded memory IP. [Online]. Available:
https://www.arm.com/products/physical-ip/embedded-memory-ip/sram.php.
16. A. J. van de Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers,
vol. 10, no. 1, pp. 8–14, Mar 1993. https://doi.org/10.1109/54.199799.
17. R. Nair, “Comments on "an optimal algorithm for testing stuck-at faults in random access
memories",” IEEE Transactions on Computers, vol. C-28, no. 3, pp. 258–261, March 1979.
https://doi.org/10.1109/TC.1979.1675331.
18. R. Dekker, F. Beenker, and L. Thijssen, “A realistic fault model and test algorithms for static
random access memories,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 6, pp. 567–572, jun 1990. https://doi.org/10.1109/43.55188.
19. IEEE, Standard for Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-2013
(Revision of IEEE Std 1149.1-2001), May 2013.
20. M. Bhushan and M. B. Ketchen, “Generation, elimination and utilization of harmonics in ring
oscillators,” in 2010 IEEE International Conference on Microelectronic Test Structures, mar
2010, pp. 108–113. https://doi.org/10.1109/ICMTS.2010.5466847.
21. The ALICE Collaboration, “Upgrade of the ALICE read-out and trigger system,” CERN, Tech.
Design Rep. CERN-LHCC-2013-019, ALICE-TDR-015, 2013. [Online]. Available: http://cds.
cern.ch/record/1603472.
22. L. Gonella, F. Faccio, M. Silvestri, S. Gerardin, D. Pantano, V. Re, M. Manghisoni, L. Ratti,
and A. Ranieri, “Total ionizing dose effects in 130-nm commercial cmos technologies for hep
experiments,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 582, no. 3, pp. 750–754, 2007,
VERTEX 2006. https://doi.org/10.1016/j.nima.2007.07.068.
23. S. M. Mahmood, “Exploring Single Event Effects in SAMPA ASIC for Time Projection Chamber (TPC) and Muon CHamber (MCH) detectors in A Large Ion Collider Experiment (ALICE),”
Ph.D. dissertation, University of Oslo, Oslo, Norway, 2019, to be published.
24. R. E. Lyons and W. Vanderkulk, “The use of triple-modular redundancy to improve computer
reliability,” IBM Journal of Research and Development, vol. 6, no. 2, pp. 200–209, apr 1962.
https://doi.org/10.1147/rd.62.0200.
25. H. Hernandez, D. Carvalho, B. Sanches, L. C. Severo, and W. V. Noije, “Current mode 1.2Gbps SLVS transceiver for readout front-end ASIC,” in 2017 IEEE International Symposium
on Circuits and Systems (ISCAS), May 2017, pp. 1–4. https://doi.org/10.1109/ISCAS.2017.
8050227.