Chapter 4
Verification and Testing
The design presented in the previous chapter has been extensively tested to guarantee
that it functions as expected once produced. This chapter presents the methodologies
and results of the verification and testing work that was completed for the first, second
and third prototype. The chapter opens with a discussion on the verification work
done on the digital design through the use of software simulations and modelling of
the design features. Methodologies in the design process to reduce the probability
of bugs appearing in the design are also discussed. The chapter continues with a
description of the acquisition system that was designed for the hardware tests and
verifications. The focus is then moved to the hardware device validation and testing
with a primary focus on the tests that have an impact on the digital design. Other
tests, e.g. analogue and ADC characterisation, have also been completed, but will
not be discussed here, as they don’t directly affect the digital design.
4.1 Functional Verification of the Digital Design
Functional verification is the task of checking that the system operates as intended
and as specified. It is one of the most important tasks in the design of ASICs, due
to the cost and turn-around time involved in their production. If an issue with the
digital design is detected after the device has been produced, it can be very difficult
to determine the cause of the issue, as there are usually no simple ways to observe
the internal operation of the design, unless specific debugging features have been
implemented for this purpose.
In contrast to analogue designs, digital designs can be almost fully verified through
computer simulations as long as the design itself is fully synchronous. In an ideal
synchronous design, the state of the system only changes when triggered by a clock
signal and so the state can be predicted by the initial state of the system and the stimuli provided. The state of an analogue or asynchronous design is more dependent on
how well the physical, manufacturing, and environmental properties are modelled.
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021
A. Velure, A Digital Signal Processor for Particle Detectors, Springer Theses,
https://doi.org/10.1007/978-3-030-71559-5_4
93
Verification and Testing
The design presented in the previous chapter has been extensively tested to guarantee
that it functions as expected once produced. This chapter presents the methodologies
and results of the verification and testing work that was completed for the first, second
and third prototype. The chapter opens with a discussion on the verification work
done on the digital design through the use of software simulations and modelling of
the design features. Methodologies in the design process to reduce the probability
of bugs appearing in the design are also discussed. The chapter continues with a
description of the acquisition system that was designed for the hardware tests and
verifications. The focus is then moved to the hardware device validation and testing
with a primary focus on the tests that have an impact on the digital design. Other
tests, e.g. analogue and ADC characterisation, have also been completed, but will
not be discussed here, as they don’t directly affect the digital design.
4.1 Functional Verification of the Digital Design
Functional verification is the task of checking that the system operates as intended
and as specified. It is one of the most important tasks in the design of ASICs, due
to the cost and turn-around time involved in their production. If an issue with the
digital design is detected after the device has been produced, it can be very difficult
to determine the cause of the issue, as there are usually no simple ways to observe
the internal operation of the design, unless specific debugging features have been
implemented for this purpose.
In contrast to analogue designs, digital designs can be almost fully verified through
computer simulations as long as the design itself is fully synchronous. In an ideal
synchronous design, the state of the system only changes when triggered by a clock
signal and so the state can be predicted by the initial state of the system and the stimuli provided. The state of an analogue or asynchronous design is more dependent on
how well the physical, manufacturing, and environmental properties are modelled.
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021
A. Velure, A Digital Signal Processor for Particle Detectors, Springer Theses,
https://doi.org/10.1007/978-3-030-71559-5_4
93