90
3 SAMPA Chip Implementation
When the device is configured to run with less than the maximum number of serial
links, the current source for the Scalable Low-Voltage Signalling (SLVS) differential
drivers [25] of the unused links are disabled to save power. The drive strength of the
used serial links can also be configured in three steps so that if the receiving device
is located close to the SAMPA, the drive strength can be decreased to lower power.
An option would have been, for applications that do not need full TMR, to have
partial or full disabling of the TMR circuitry to save power. However, due to the way
the TMR was implemented, this could not be easily be implemented.
The power consumption of the device operating with different clock frequencies
is listed in Table 3.5, it can be seen that the power scales linearly, mainly with the
main operating ADC clock.
References
1. H. D. H. Herrera, “Noise and PSRR improvement technique for TPC readout front-end in
CMOS technology,” Ph.D. dissertation, Escola Politécnica, São Paulo, Brazil, 2015. [Online].
Available: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05072016-151016/.
2. G. Gramegna, P. O’Connor, P. Rehak, and S. Hart, “CMOS preamplifier for low-capacitance
detectors,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators,
Spectrometers, Detectors and Associated Equipment, vol. 390, no. 1, pp. 241–250, 1997. https://
doi.org/10.1016/S0168-9002(97)00390-2.
3. C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a
monotonic capacitor switching procedure,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4,
pp. 731–740, Apr 2010. https://doi.org/10.1109/jssc.2010.2042254.
4. M. Arora, The Art of Hardware Architecture: Design Methods and Techniques for Digital
Circuits. New York, NY: Springer New York, 2012. [Online]. Available: https://doi.org/10.
1007/978-1-4614-0397-5_2.
5. C. E. Cummings, “Asynchronous & synchronous reset design techniques - part deux,” in
Synopsis User Group Meeting, 2003.
6. NXP Semiconductors, I2C-bus specification and user manual, 6th ed., April 2014.
7. Microchip Technology Inc., 24LC16B Datasheet, 2016. [Online]. Available: https://www.
microchip.com/datasheet/24LC16B.
8. E. G. Garcia and R. E. Bosch, “Low power optimization of an IIR for tail cancellation in High
Energy Physics applications,” in 2009 Ph.D. Research in Microelectronics and Electronics,
July 2009, pp. 28–31. https://doi.org/10.1109/RME.2009.5201329.
9. T. Naaranoja, “Digital Signal Processing for Particle Detectors in Front-End Electronics,”
Master Thesis, University of Helsinki, Helsinki, Finland, 2014. [Online]. Available: http://hdl.
handle.net/10138/135874.
10. K. Münning, “Impact of BC2 and BC3 on simulated data, comparison,” SAMPA MPW2 design
review II Meeting. [Online]. Available: https://indico.cern.ch/event/382908/contributions/
1809834/attachments/763500/1047483/Slides-20150401-SAMPA-Filter-Comparison.pdf.
11. The ALICE TPC Collaboration, ALICE TPC Readout Chip User Manual v. 0.2, CERN,
2002. [Online]. Available: http://ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc/doc/ALTRO_
CHIP/UserManual_draft_02.pdf.
12. S. Klewin, “Length-limited Huffman coding,” TPC CRU Meeting, 2015. [Online].
Available: https://indico.cern.ch/event/453573/contributions/1951400/attachments/1169252/
1687190/klewin_2015_10_13.pdf.
13. C. E. Cummings, “Simulation and synthesis techniques for asynchronous FIFO design,” in
Synopsis User Group Meeting, 2002.
3 SAMPA Chip Implementation
When the device is configured to run with less than the maximum number of serial
links, the current source for the Scalable Low-Voltage Signalling (SLVS) differential
drivers [25] of the unused links are disabled to save power. The drive strength of the
used serial links can also be configured in three steps so that if the receiving device
is located close to the SAMPA, the drive strength can be decreased to lower power.
An option would have been, for applications that do not need full TMR, to have
partial or full disabling of the TMR circuitry to save power. However, due to the way
the TMR was implemented, this could not be easily be implemented.
The power consumption of the device operating with different clock frequencies
is listed in Table 3.5, it can be seen that the power scales linearly, mainly with the
main operating ADC clock.
References
1. H. D. H. Herrera, “Noise and PSRR improvement technique for TPC readout front-end in
CMOS technology,” Ph.D. dissertation, Escola Politécnica, São Paulo, Brazil, 2015. [Online].
Available: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05072016-151016/.
2. G. Gramegna, P. O’Connor, P. Rehak, and S. Hart, “CMOS preamplifier for low-capacitance
detectors,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators,
Spectrometers, Detectors and Associated Equipment, vol. 390, no. 1, pp. 241–250, 1997. https://
doi.org/10.1016/S0168-9002(97)00390-2.
3. C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a
monotonic capacitor switching procedure,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4,
pp. 731–740, Apr 2010. https://doi.org/10.1109/jssc.2010.2042254.
4. M. Arora, The Art of Hardware Architecture: Design Methods and Techniques for Digital
Circuits. New York, NY: Springer New York, 2012. [Online]. Available: https://doi.org/10.
1007/978-1-4614-0397-5_2.
5. C. E. Cummings, “Asynchronous & synchronous reset design techniques - part deux,” in
Synopsis User Group Meeting, 2003.
6. NXP Semiconductors, I2C-bus specification and user manual, 6th ed., April 2014.
7. Microchip Technology Inc., 24LC16B Datasheet, 2016. [Online]. Available: https://www.
microchip.com/datasheet/24LC16B.
8. E. G. Garcia and R. E. Bosch, “Low power optimization of an IIR for tail cancellation in High
Energy Physics applications,” in 2009 Ph.D. Research in Microelectronics and Electronics,
July 2009, pp. 28–31. https://doi.org/10.1109/RME.2009.5201329.
9. T. Naaranoja, “Digital Signal Processing for Particle Detectors in Front-End Electronics,”
Master Thesis, University of Helsinki, Helsinki, Finland, 2014. [Online]. Available: http://hdl.
handle.net/10138/135874.
10. K. Münning, “Impact of BC2 and BC3 on simulated data, comparison,” SAMPA MPW2 design
review II Meeting. [Online]. Available: https://indico.cern.ch/event/382908/contributions/
1809834/attachments/763500/1047483/Slides-20150401-SAMPA-Filter-Comparison.pdf.
11. The ALICE TPC Collaboration, ALICE TPC Readout Chip User Manual v. 0.2, CERN,
2002. [Online]. Available: http://ep-ed-alice-tpc.web.cern.ch/ep-ed-alice-tpc/doc/ALTRO_
CHIP/UserManual_draft_02.pdf.
12. S. Klewin, “Length-limited Huffman coding,” TPC CRU Meeting, 2015. [Online].
Available: https://indico.cern.ch/event/453573/contributions/1951400/attachments/1169252/
1687190/klewin_2015_10_13.pdf.
13. C. E. Cummings, “Simulation and synthesis techniques for asynchronous FIFO design,” in
Synopsis User Group Meeting, 2002.